BEOL Interconnect Airgap Isolation for Lower RC Delay
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Solution Overview
Problem
The challenge in semiconductor device technology is to reduce resistive-capacitance (RC) in BEOL interconnect structures while maintaining mechanical stability, as conventional low-k dielectric materials fail to provide sufficient time-dependent dielectric breakdown (TDDB) benefits, and airgaps between conducting wires can compromise durability.
Innovation Solution
Embedding airgaps between metal lines in BEOL interconnect structures using a dielectric cap to pinch-off spaces between dielectric liners, formed by depositing a dielectric liner, masking layers, and selectively removing organic planarizing materials to create controlled airgaps, which reduces parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If airgaps are introduced between metal lines to reduce parasitic capacitance and resistance, then RC delay is reduced, but mechanical stability and durability are compromised
Solution Approach 1:
The patent uses a composite structure combining dielectric material and airgap. The dielectric liner provides mechanical support and stress relief, while the airgap reduces parasitic capacitance. This composite approach allows the structure to benefit from both the mechanical properties of solid material and the electrical properties of air, resolving the contradiction between RC reduction and mechanical stability.
Solution Approach 2:
The airgap is not introduced throughout the entire interconnect structure but only in specific regions between metal lines where capacitance reduction is most beneficial. The dielectric material remains in places where mechanical support is needed. This localized application of airgaps allows RC delay reduction while maintaining overall structural integrity.
2Loss of energy
If low-k dielectric materials are used to reduce RC delay, then parasitic capacitance is reduced, but time-dependent dielectric breakdown (TDDB) resistance is insufficient
Solution Approach 1:
The patent changes the dielectric constant parameter by introducing airgaps (k≈1) instead of using low-k dielectric materials (k>2.5). This parameter change achieves lower parasitic capacitance while avoiding the TDDB reliability issues associated with low-k materials, as air does not suffer from dielectric breakdown over time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical performance by reducing RC delay without compromising mechanical stability, allowing for IC scaling with improved RC performance and controllable airgap sizes.
Implementation Method 1
a dielectric cap above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between the plurality of metal lines
Data Source
AI summary
Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.