Air-Gap Interconnect Layout for Dense BEOL RC Delay Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits are scaled down, the increased density and reduced spacing between conductive features lead to increased parasitic capacitance, which in turn increase power consumption and time delay, necessitating the use of low-k dielectrics to improve device performance.
Innovation Solution
The formation of air-gaps in dielectric materials between conductive features reduces the effective dielectric constant, achieved by etching a selective portion of the dielectric material to create trenches, forming sacrificial spacers, and filling these with conductive material while maintaining spacers at desired air-gap positions, thereby reducing capacitance and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between conductive features is reduced to increase density, then the device integration is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent introduces air-gaps (porous structures) between conductive features in the interconnect structure. These air-gaps have a dielectric constant of nearly 1, replacing the solid dielectric material and significantly reducing parasitic capacitance while maintaining reduced spacing between conductors, thus resolving the contradiction between high density and low capacitance.
2Object-generated harmful factors
If low-k dielectric materials are used to reduce parasitic capacitance, then the device performance is improved, but the dielectric constant is reduced
Solution Approach 1:
The patent creates a composite interconnect structure combining solid dielectric material with air-gap regions. This composite approach leverages the beneficial properties of both: the solid dielectric provides mechanical strength and reliability, while the air-gaps provide extremely low parasitic capacitance, thus resolving the contradiction between capacitance reduction and reliability maintenance.
3Object-generated harmful factors
If air-gaps are formed by etching dielectric material, then the parasitic capacitance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent forms sacrificial spacers before filling the trenches with conductive material. These spacers are deposited and patterned in advance to define the precise locations where air-gaps should eventually form. This preliminary action simplifies the overall process by establishing the air-gap geometry early, avoiding complex subsequent etching steps through the completed interconnect structure.
Solution Approach 2:
The sacrificial spacers act as intermediary structures that temporarily occupy the space where air-gaps will eventually form. These spacers are deposited conformally, then selectively removed after conductor filling, leaving clean air-gap regions. This intermediary approach simplifies manufacturing by using a temporary placeholder rather than requiring direct etching of the dielectric after conductor deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, improves device performance by lowering the k-value, and minimizes damage and contamination to the dielectric material, while allowing better via alignment and reduced RC delay in Back-end of Line (BEOL) structures.
Implementation Method 1
Large pores, also referred to as air-gaps, can provide an extremely low-k dielectric between the two conductive features
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.