BEOL Anti-Fuse Structures for Gate-Last Semiconductor Devices
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Solution Overview
Problem
Conventional metal fuses in semiconductor devices require high programming current and occupy significant space, making them inefficient for modern gate last technologies with shrinking transistor dimensions.
Innovation Solution
The development of an anti-fuse structure utilizing dielectric breakdown techniques, where a second electrode is formed concentrically around a first electrode with a dielectric material in between, allowing for programming at low power supply voltages and reduced semiconductor real estate, with vias connecting the electrodes to enable current flow upon dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal fuses are formed in BEOL, then fuse functionality is achieved, but programming current requirement increases and space occupation increases
Solution Approach 1:
The patent inverts the conventional fuse approach by using anti-fuse structures that rely on dielectric breakdown rather than metal filament formation. This inversion allows programming at lower voltages (5-10V vs. higher currents) while maintaining fuse functionality through the irreversible breakdown of the interlayer dielectric material between electrodes.
Solution Approach 2:
The patent changes the programming mechanism from high-current metal fuse breaking to low-voltage dielectric breakdown. By altering the fundamental programming parameter from current-intensive to voltage-controlled breakdown, the invention achieves fuse functionality with reduced energy consumption and lower programming requirements.
2Reliability
If conventional metal fuses are formed in BEOL, then fuse functionality is achieved, but space occupation increases
Solution Approach 1:
The patent embeds the fuse structure within existing BEOL metallization layers and interlayer dielectric materials. The anti-fuse structure nests electrodes within the ILD, utilizing the existing semiconductor device architecture rather than requiring separate dedicated space, thereby reducing overall space occupation while maintaining fuse functionality.
Solution Approach 2:
The patent transitions from planar metal fuse structures to vertically-integrated anti-fuse structures that utilize the third dimension (vertical stacking of metallization layers and ILD). This dimensional change allows fuse functionality to be achieved within the existing vertical architecture of BEOL, reducing lateral space requirements.
3Adaptability or versatility
If polysilicon gate electrodes are replaced with metal electrodes, then gate last technology is enabled, but polysilicon fuses can no longer be built
Solution Approach 1:
The patent creates a universal anti-fuse structure that works with metal gate electrodes in gate-last technologies. The BEOL-formed anti-fuse structure serves multiple functions: it provides fuse functionality compatible with metal gates, utilizes existing metallization layers, and can be programmed through dielectric breakdown, thereby enabling adaptability to gate-last technology while maintaining ease of manufacture through standard BEOL processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the programming voltage and space requirements, enabling efficient and reliable formation of fuse structures that are programmable at lower power and occupy less space compared to conventional metal fuses.
Implementation Method 1
breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the device
Data Source
AI summary
An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.


