BEOL Interconnect Barrier Layout for Low-Resistance Copper Contacts
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Solution Overview
Problem
Copper diffusion in semiconductor devices leads to increased resistivity and semiconductor device failures due to high electromigration rates, while barrier layers used to prevent diffusion increase contact resistance and surface roughness.
Innovation Solution
Forming a barrier layer on the sidewalls of conductive structures in semiconductor devices without covering the top surface, using techniques such as surface treatment and graphene layers to prevent barrier layer formation, and employing metal liners to improve copper gap filling and adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed to prevent copper diffusion, then copper diffusion is reduced, but contact resistance and surface roughness increase
Solution Approach 1:
The patent applies different treatments to different regions of the conductive structure. The barrier layer is selectively formed only on the sidewalls of the conductive structure, while the top surface is kept free of barrier layer material through surface treatment processes. This local differentiation allows copper diffusion prevention on sidewalls without introducing contact resistance at the top surface contact interface.
Solution Approach 2:
The barrier layer formation process is segmented into selective regions. The sidewall region receives barrier layer deposition for diffusion prevention, while the top surface region is treated separately to remain barrier-layer-free. This segmentation resolves the contradiction by providing barrier functionality only where diffusion occurs, eliminating the harmful effect on contact interfaces.
2Reliability
If a barrier layer is formed to prevent copper diffusion, then copper diffusion is reduced, but surface roughness increases
Solution Approach 1:
The surface treatment process creates local quality differences by preventing barrier layer material from depositing on the top surface while allowing it on sidewalls. This selective formation maintains smooth top surfaces for subsequent processing and device performance, while still providing diffusion barriers where geometrically necessary.
3Ease of manufacture
If metal liners are used to improve copper gap filling, then adhesion and gap filling improve, but device complexity increases
Solution Approach 1:
The metal liner is deposited in advance as a preliminary layer before copper filling. This preliminary action prepares the surface for optimal copper adhesion and enables effective gap filling by providing a nucleation layer that promotes uniform copper deposition, even in high-aspect-ratio structures.
Solution Approach 2:
The patent employs a composite structure consisting of multiple functional layers: barrier layer on sidewalls, metal liner at the base, and copper fill. This composite material approach combines the diffusion-blocking properties of barrier materials with the adhesion and conductivity properties of metal liners and copper, achieving superior overall performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces contact resistance and surface roughness, enhancing semiconductor device performance by maintaining low resistivity and preventing copper diffusion.
Implementation Method 1
Copper diffusion in semiconductor devices leads to increased resistivity and semiconductor device failures due to high electromigration rates, while barrier layers used to prevent diffusion increase contact resistance and surface roughness
Implementation Method 2
using techniques such as surface treatment and graphene layers to prevent barrier layer formation
Implementation Method 3
using techniques such as surface treatment and graphene layers to prevent barrier layer formation
Implementation Method 4
employing metal liners to improve copper gap filling and adhesion
Data Source
AI summary
Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.