Buffer Layer for BEOL IMD Adhesion

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Solution Overview

Problem

Conventional back-end-of-line (BEOL) stacks in integrated circuits face reliability issues due to high stress in thicker inter-metal dielectric (IMD) layers, which can lead to delamination and cracks, especially in advanced ICs used for power applications where thick metal lines are required to minimize resistive loss.

Innovation Solution

Incorporating a buffer layer on the top surface of the upper conductive line in the BEOL stack, which is thicker than the lower conductive lines, to improve adhesion of the upper IMD layer and reduce stress, thereby enhancing the reliability of the BEOL stack.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the upper IMD layer is made thicker to cover the thick upper conductive line and balance stress, then the coverage and stress balancing are improved, but the adhesion deteriorates due to high stress leading to delamination and cracks

Engineering Contradiction:
ImproveIMD layer coverage areaVSAvoidIMD layer adhesion
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

A buffer layer is introduced as an intermediary between the upper conductive line and the upper IMD layer. This buffer layer has a stress profile that transitions from compressive at the conductive line interface to tensile at the IMD layer interface, effectively mediating the stress between these two layers and preventing delamination and cracks while maintaining adequate coverage.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The stress state of the IMD layer is changed by introducing the buffer layer, which transforms the uniform high compressive stress into a gradient stress distribution. The buffer layer creates a transition from compressive stress near the conductive line to tensile stress near the IMD layer, fundamentally changing the stress parameters to improve adhesion.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If the upper conductive line is made thicker to minimize resistive loss, then the power consumption is reduced, but the stress in the subsequent IMD layer increases leading to delamination and cracks

Engineering Contradiction:
Improveresistive lossVSAvoidIMD layer integrity
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The buffer layer serves as a stress-mediating intermediary that allows the upper conductive line to maintain its thick configuration for low resistive loss while protecting the IMD layer from the harmful stress effects. The buffer layer absorbs and redistributes the stress, preventing it from concentrating in the IMD layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The buffer layer converts the harmful compressive stress generated by the thick conductive line into a beneficial gradient stress distribution. The compressive stress at the conductive line interface is transformed into a controlled transition that results in tensile stress at the IMD layer interface, which is less harmful and can even improve adhesion.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The buffer layer effectively improves the adhesion of the upper IMD layer to the conductive lines, reducing the risk of delamination and cracks, and enhances the overall reliability of the BEOL stack while maintaining low resistive loss.

Implementation Method 1

The buffer layer is configured to improve adhesion of the upper IMD layer to the upper conductive line stack

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS11282744B2Enhanced intermetal dielectric adhesion
Publication Date: 2022.03.22 SYST ON SILICON MFG PTE
  • US11282744B2 patent drawing
  • US11282744B2 patent drawing
  • US11282744B2 patent drawing

AI summary

Device and method of forming the device are disclosed. A semiconductor device includes a back-end-of-line dielectric (BEOL) with a plurality of IMD levels over a substrate processed with front-end-of-line components. The BEOL includes an upper IMD level and upper metal lines, with a buffer layer over the upper metal lines. The buffer layer improves adhesion of the upper IMD layer which covers the upper metal lines. Improving the adhesion of the upper IMD layer improves the reliability of the device.