BEOL Capacitor Air Gap Structure for Density Scaling
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Solution Overview
Problem
As technology scales, the capacitance density of vertical natural capacitors in integrated circuits decreases due to increased circuit density, necessitating a solution to enhance capacitance while maintaining device scaling.
Innovation Solution
The method involves forming wiring lines with air gaps by depositing a capping material between them, followed by opening these gaps and filling them with conductive material, which is achieved through a combination of copper etch back and air gap processes, allowing for increased capacitance density using ultra-low dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit density is increased to maintain device scaling, then device density improves, but capacitance density drops
Solution Approach 1:
The patent transitions from planar capacitors to vertical three-dimensional capacitors by stacking multiple capacitor layers (e.g., five layers shown in FIG. 5) along the vertical axis. This dimensional change allows capacitance to be accumulated in the vertical direction rather than being constrained to the horizontal plane, thereby maintaining capacitance density even as circuit density increases and devices are scaled down.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor layers are stacked vertically within a compact footprint. Each capacitor layer consists of alternating conductive plates and dielectric layers, with lower capacitors nested beneath upper capacitors. This nesting approach maximizes the use of vertical space to achieve high capacitance density without increasing the horizontal area occupied by the capacitor structure.
2Reliability
If vertical natural capacitors are used in BEOL processes, then on-chip capacitance is achieved, but capacitance density decreases with technology scaling
Solution Approach 1:
The patent changes the key parameter of capacitance accumulation from two-dimensional planar expansion to three-dimensional vertical stacking. By forming multiple capacitor layers at different heights (e.g., capacitors 42-46 in FIG. 5) with conductive plates separated by dielectric layers, the total capacitance is the sum of individual layer capacitances. This parameter change enables capacitance density to increase or at least be maintained despite technology scaling, as the vertical dimension provides additional capacitance accumulation space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables device scaling with increased capacitance density, effectively addressing the capacitance drop issue in back-end-of-line capacitors by creating a vertical natural capacitor structure with enhanced performance.
Implementation Method 1
forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material
Implementation Method 2
depositing conductive material within the opened air gap
Data Source
AI summary
Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.