Carrier-Wafer ESD Array With BEOL Routing for Deep-Submicron ICs

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Solution Overview

Problem

Integrated circuits (ICs) face challenges in protecting against electrostatic discharge (ESD) events due to high power dissipation and area constraints, leading to potential damage and inefficiencies in existing ESD protection networks, especially in deep sub-micron processes.

Innovation Solution

Implementing an ESD protection network on a carrier wafer with patterned ESD protection circuits, including diodes and power clamp circuits, that divert ESD pulses and reduce on-chip layout area by routing ESD signals through a power delivery network, using conductive materials like copper and aluminum, and integrating these circuits in a wafer stack with thermal compression bonding and BEOL fabrication processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an ESD protection network is implemented on the IC chip, then ESD protection is provided, but on-chip area is consumed

Engineering Contradiction:

ImproveESD protectionVSAvoidon-chip area

Core Design Contradiction:

ReliabilityVSArea of moving object

Solution Approach 1:

The ESD protection network is extracted from the IC chip and relocated to the carrier wafer. The carrier wafer includes an ESD protection network that is electrically connected to the IC chip through the power delivery network, thereby providing ESD protection while freeing up on-chip area for other functional circuits.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If an ESD protection network is implemented on the IC chip, then ESD protection is provided, but the design is limited to a specific semiconductor fabrication technology

Engineering Contradiction:

ImproveESD protectionVSAvoidfabrication technology compatibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The carrier wafer is designed to be compatible with multiple semiconductor fabrication technologies including deep sub-micron processes. The ESD protection network on the carrier wafer can serve various IC chips fabricated using different technologies, making the solution universally applicable across multiple fabrication processes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If ESD protection circuits are integrated on-chip, then protection is provided, but power dissipation increases

Engineering Contradiction:

ImproveESD protectionVSAvoidpower dissipation

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The ESD protection network is extracted from the IC chip and placed on the carrier wafer. This separation reduces the power dissipation impact on the IC chip itself, as the ESD protection circuits operate independently on the carrier wafer while still protecting the IC chip through the power delivery network.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS11855076B2Electrostatic discharge (ESD) array with back end of line (BEOL) connection in a carrier wafer

Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.