BEOL Die Stitching for High-Density Multi-Die Interconnects
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Solution Overview
Problem
Current IC manufacturing methods face limitations in interconnecting multiple dies efficiently, particularly in forming high-density connections and managing die sizes beyond the standard reticle size, leading to reduced yield and increased defects.
Innovation Solution
The implementation of die stitching techniques that form die-to-die routing within the BEOL build-up structure, allowing for flexible interconnection of dies with pre-formed or customized metallic seals, enabling high-density interconnects and dynamic die grouping, and providing additional protection through hermetic sealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard reticle size (5 inch plate) is used for IC manufacturing, then manufacturing process is simplified, but die size lateral dimension is limited to approximately 32 mm
Solution Approach 1:
The patent divides a large die into multiple smaller die segments that can be manufactured using standard reticle sizes. These segmented dies are then interconnected through the BEOL build-up structure to form a functional multi-chip module, effectively overcoming the reticle size limitation while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The patent transitions from 2D planar interconnection to 3D vertical interconnection by forming die-to-die routing through the BEOL build-up structure. This allows multiple die to be stacked and interconnected in the vertical dimension, enabling larger effective die sizes without requiring larger reticle areas
2Reliability
If multiple die are interconnected using traditional packaging methods, then die-to-die connections are established, but connection density is reduced and latency increases
Solution Approach 1:
The patent merges the interconnection function into the BEOL build-up structure itself, combining the die stacking process with the routing formation process. This integration creates direct die-to-die connections through the build-up layers, eliminating the need for separate packaging interconnection steps and reducing signal latency
Solution Approach 2:
The patent performs die-to-die routing formation during the BEOL build-up process before final packaging. By preliminarily establishing the interconnection paths through the build-up structure, the patent enables direct connections that reduce signal travel distance and latency compared to post-packaging interconnection methods
3Productivity
If die size is increased to reduce I/O area, then manufacturing flexibility is improved, but defect density increases and yield decreases
Solution Approach 1:
The patent segments large dies into multiple smaller dies that can be manufactured with lower defect densities. By using standard reticle sizes to produce smaller individual dies and then interconnecting them through BEOL routing, the patent achieves high wafer utilization while maintaining lower defect rates compared to manufacturing fewer large dies
Solution Approach 2:
The patent changes the effective die size parameter by creating virtual large dies through the interconnection of multiple physical small dies. This parameter transformation allows the system to achieve the I/O area benefits of large dies while maintaining the manufacturing quality benefits of small dies
4Object-affected harmful factors
If hermetic sealing is applied to protect die, then environmental protection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the hermetic sealing function with the BEOL build-up structure by forming the seal as an integrated part of the build-up layers. This integration eliminates the need for separate sealing components and processes, providing environmental protection while maintaining manufacturing simplicity
Data Source
AI summary
Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.


