BEOL Dielectric Elastic Modulus Variation for CPI Resistance
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Solution Overview
Problem
The mechanical strength of low-k dielectric materials used in the back-end-of-line (BEOL) portion of integrated circuit (IC) devices is compromised due to increased porosity, making them susceptible to mechanical damage from Chip Package Interaction (CPI) caused by thermal expansion mismatches and local stress introduced by packaging technologies, especially in sub-32 nm technology and 3D chip stacking.
Innovation Solution
A method is introduced where a mask layer is applied to the BEOL stack during fabrication, allowing for localized changes in the elastic modulus of dielectric materials through treatments such as UV radiation, pore-filling, or porogen removal, specifically in areas not covered by the mask, to enhance mechanical properties without affecting electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If porosity of dielectric material is increased to lower k-value, then RC delay is reduced, but mechanical strength is reduced making material susceptible to mechanical damage
Solution Approach 1:
The patent applies different porosity levels to different regions of the dielectric layer. The first region (under stress-prone areas like Cu pillars and TSVs) has lower porosity (higher mechanical strength), while the second region has higher porosity (lower k-value). This spatial differentiation resolves the contradiction by allowing each region to have optimized properties for its specific function.
Solution Approach 2:
The dielectric layer is segmented into multiple regions with different porosity characteristics. The patent divides the BEOL structure into stress-prone areas requiring mechanical reinforcement and non-stress areas optimized for electrical performance, creating distinct functional zones within the same dielectric layer.
2Strength
If adhesion layers or crack stoppers are added to address CPI problems, then mechanical strength is improved, but device complexity increases
Solution Approach 1:
The patent makes the dielectric layer itself multi-functional by giving it both mechanical support function (through low-porosity regions) and electrical insulation function (through high-porosity regions). This eliminates the need for separate adhesion layers or crack stoppers, as the dielectric layer performs both roles simultaneously.
Solution Approach 2:
The patent merges the mechanical reinforcement function and electrical insulation function into a single dielectric layer structure. By varying porosity within the same layer rather than adding separate layers, the solution combines multiple functions into one component, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach strengthens specific areas of the dielectric material in the BEOL portion, reducing the risk of mechanical failure and improving the overall mechanical integrity of the IC device while maintaining low dielectric constant and porosity for reduced RC delay.
Implementation Method 1
The UV radiation treatment may comprise using essentially monochromatic UV radiation, with a wavelength between 120 nm and 200 nm
Implementation Method 2
applying a liquid pore-filling material to the exposed portion (s) of the stack surface area, so as to allow said liquid to penetrate the pores of the dielectric material
Implementation Method 3
a heating step to a temperature above the glass-forming temperature of the pore-filling material, thereby increasing the elastic modulus
Implementation Method 4
a porogen-removing treatment, configured to remove at least an amount of said porogen from the pores in the exposed portion(s) of the dielectric layer
Data Source
AI summary
The present invention is related to a method for producing an integrated circuit device, comprising a Front-end-of-line (FEOL) portion and a Back-end-of-line (BEOL) portion (102). The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within said dielectric layers. In a device according to the invention, in at least some of the metallization layers of the BEOL stack, the elastic modulus of the dielectric material varies from one area of the layer to one or more other areas of the layer. In the method of the invention, a mask layer (21) is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, said mask layer covering portions of the stack area and exposing other portions of said area. Then a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in the areas not covered by the mask layer.