BEOL Dielectric Planarization via Polishing Stop Layer
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Solution Overview
Problem
Conventional chemical mechanical polishing (CMP) processes are unreliable for planarizing topological surfaces with large elevation disparities in back-end-of-line (BEOL) dielectrics during semiconductor fabrication, leading to potential fabrication defects.
Innovation Solution
A method involving the formation of a BEOL dielectric stack with a CMP process to create a planar top surface across both memory and non-memory regions, using a chemical mechanical polishing process to remove step structures in the upper dielectric layer, ensuring uniform planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMP process is used to planarize BEOL dielectric with large elevation disparities, then surface planarization is attempted, but over-polishing occurs in unelevated portions leading to fabrication defects
Solution Approach 1:
The patent applies local quality by making the CMP process selective to different regions. A polishing stop layer is introduced that has different polishing rates or stopping characteristics in memory regions versus non-memory regions. This allows the CMP process to automatically stop at different depths in different regions, preventing over-polishing in flat areas while adequately planarizing elevated areas with storage units.
Solution Approach 2:
The patent introduces a polishing stop layer as an intermediary element between the dielectric layer and the underlying structure. This stop layer acts as a mediator that controls the CMP process by providing a distinct polishing endpoint. The stop layer has specific material properties that differ from the dielectric layer, enabling precise control of material removal and preventing over-polishing defects.
2Manufacturing precision
If CMP process removes large surface elevation in one portion of BEOL dielectric layer, then elevated portions are planarized, but unelevated portions are over-polished
Solution Approach 1:
The polishing stop layer provides location-dependent polishing characteristics. In elevated portions containing storage units, the stop layer allows controlled material removal to achieve planarization. In unelevated portions without storage units, the stop layer acts as a barrier that prevents further polishing, thus avoiding over-polishing defects. This local differentiation resolves the contradiction between achieving elevation uniformity and preventing harmful over-polishing.
Solution Approach 2:
The polishing stop layer is deposited in advance before the CMP process. This preliminary action prepares the surface with predetermined polishing characteristics that will control the subsequent CMP process. The stop layer is specifically designed with material properties that enable it to stop the polishing process at the desired depth, preventing over-polishing before it can occur.
3Manufacturing precision
If storage units are formed in memory region of ILD level, then memory structures are created, but large step height is created between memory and non-memory regions
Solution Approach 1:
The patent changes the physical parameters of the dielectric structure by introducing a polishing stop layer with different material properties. This layer has distinct polishing rates compared to the main dielectric layer, enabling differential material removal. The parameter change in material composition and polishing behavior allows the process to accommodate the large step heights created by storage units while achieving a planar final surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves control and uniformity of planarization processes, preventing over-polishing and enhancing the reliability of BEOL dielectric planarization, thereby reducing fabrication defects.
Implementation Method 1
performing a chemical mechanical polishing (CMP) process to remove the step structure of the upper dielectric layer
Data Source
AI summary
A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.