BEOL Standard Cell Layout Using Removable Dummy Metal Lines
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Solution Overview
Problem
The existing full-track design for BEOL regions in IC devices increases process margin but results in higher capacitance due to increased metal content, whereas the non-full-track design has lower capacitance but reduced process margin.
Innovation Solution
A method is introduced to convert a non-full-track standard cell into a full-track standard cell by adding dummy metal lines, performing metal patterning, and then removing the dummy metal lines to revert back to the non-full-track design, thereby enhancing process margin without increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a full-track design is used in the BEOL region, then process margin is improved, but capacitance increases due to increased metal content
Solution Approach 1:
The patent applies preliminary action by adding dummy metal lines to the standard cell design before performing metal patterning. This creates a full-track design that provides better process margin during manufacturing. The dummy lines are strategically placed in signal-line areas to ensure complete metal coverage, which improves the robustness of the patterning process without affecting the final functional design after dummy line removal.
Solution Approach 2:
The patent utilizes parameter changes by temporarily modifying the metal line configuration during the manufacturing process. The dummy metal lines change the physical state of the standard cell from non-full-track to full-track during patterning, providing process margin benefits. After patterning completes successfully, the dummy lines are removed through selective etching, returning the design to its original non-full-track configuration with lower capacitance.
2Quantity of substance
If a non-full-track design is used in the BEOL region, then capacitance is reduced, but process margin decreases
Solution Approach 1:
The patent applies preliminary action by temporarily adding dummy metal lines to create a full-track design before metal patterning. This preliminary modification provides the necessary process margin during manufacturing while maintaining the advantage of lower capacitance in the final design. The dummy lines are removed after patterning to restore the non-full-track configuration.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the metal line configuration through the addition and subsequent removal of dummy lines. During the critical patterning phase, the design parameter changes from non-full-track to full-track to improve process margin. After patterning, the parameter reverts to non-full-track to minimize capacitance, effectively using parameter transformation to resolve the contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the process margin during metal patterning while minimizing the capacitance penalty associated with the full-track design, thereby improving the manufacturability and performance of IC devices.
Implementation Method 1
The method may include removing the dummy metal lines by performing a subtractive metal etch of the dummy metal lines
Data Source
AI summary
Methods of forming a back-end-of-line (BEOL) region of an integrated circuit (IC) device are provided. A method of forming a BEOL region of an IC device includes converting a non-full-track standard cell designed for the BEOL region to a full-track standard cell by adding dummy metal lines to the non-full-track standard cell. The method includes removing the dummy metal lines. Moreover, the method includes forming top vias after removing the dummy metal lines.