BEOL Three-Terminal FeFET Cell for Multi-Level Non-Volatile Memory
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Solution Overview
Problem
Existing CMOS integrated circuits face trade-offs between on-chip SRAM's high performance and low cost-effectiveness and off-chip Flash memory's low performance and high density, with FEOL FeFET implementations facing area constraints and reliability issues due to silicon-based charge trapping effects.
Innovation Solution
A three-terminal, multi-level non-volatile memory cell with a ferroelectric field-effect transistor (FeFET) located in the BEOL, comprising a cascade of nMOS, ox-FeFET, and pMOS FETs, allowing for enhanced multi-level switching and reduced crosstalk, using oxide channels like tungsten oxide and hafnium oxide-based ferroelectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If on-chip SRAM is used for high performance memory, then speed and latency are improved, but cost effectiveness and density deteriorate
Solution Approach 1:
The patent changes the fundamental parameter of memory technology from volatile (SRAM, DRAM) to non-volatile ferroelectric memory. By using ferroelectric materials with multi-level polarization states, the invention achieves high density storage while maintaining fast access speeds comparable to volatile memory, thus resolving the contradiction between speed and density
Solution Approach 2:
The patent employs composite material structures including ferroelectric HfO2 layers combined with metal gates and oxide channels. This composite approach enables the memory cell to achieve both the speed characteristics of traditional CMOS and the density benefits of non-volatile storage, simultaneously improving speed and density
2Quantity of substance
If off-chip Flash memory is used for high density storage, then capacity is improved, but performance and speed deteriorate
Solution Approach 1:
The patent fundamentally changes the memory technology parameter from Flash-based charge trapping to ferroelectric polarization. This enables high capacity storage with significantly improved write speeds and lower power consumption, as ferroelectric switching occurs at much lower voltages and faster timescales than Flash programming
Solution Approach 2:
The patent introduces multi-level polarization states as an additional dimension of data storage. By utilizing different polarization magnitudes and orientations in the ferroelectric material, the invention achieves high capacity storage similar to Flash but with the speed characteristics of volatile memory
3Quantity of substance
If FEOL FeFET is used for non-volatile memory, then memory density is improved, but area constraints and reliability issues worsen due to silicon-based charge trapping effects
Solution Approach 1:
The patent extracts the FeFET structure from the FEOL process and relocates it to the BEOL. This separation removes the device from the constrained front-end process environment, eliminating area constraints and allowing the use of more reliable oxide-based channels instead of silicon, thereby improving reliability while maintaining high density
Solution Approach 2:
The patent replaces the expensive and unreliable silicon-based charge trapping mechanism with a simpler, more reliable oxide-based ferroelectric mechanism. The oxide channel FeFET uses abundant oxide materials and achieves comparable or superior density with significantly improved reliability and lower manufacturing cost
4Quantity of substance
If multi-level programming is implemented to increase storage capacity, then memory density is improved, but programming complexity and energy consumption worsen
Solution Approach 1:
The patent applies partial programming actions to achieve multi-level states. By using incremental step pulse programming (ISPP) where each pulse contributes a portion of the total polarization change, the system can program multiple bits per cell with moderate energy per step, reducing total programming energy compared to single-step multi-level programming
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The BEOL FeFET design enhances memory density, energy efficiency, and endurance by up to two orders of magnitude, providing high performance, low latency, and cost-effective non-volatile memory with up to 200 levels per cell and reduced interconnect requirements.
Implementation Method 1
a ferroelectric material (e.g., a hafnium oxide (HfO2)-based material) disposed on the ox-channel
Data Source
AI summary
Three-terminal, multi-level non-volatile memory cells having a FeFET in the BEOL are provided. In one aspect, a memory cell includes: a cascade of elements all sharing a common gate terminal and, via the common gate terminal, a common VG, where the cascade of elements includes: an nMOS FET; an ox-FeFET located in the BEOL that is connected to the nMOS FET; and a pMOS FET that is connected to the ox-FeFET. Multi-cell memory implementations thereof, and methods for operating the present memory cells are also provided.