BEOL Ferroelectric Data Backup Unit for SRAM Footprint Reduction
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Solution Overview
Problem
Existing memory devices face challenges in efficiently restoring data to SRAM cells without increasing the footprint on the substrate, particularly due to the placement of data backup units within the FEOL structure, which limits device density and performance.
Innovation Solution
The memory device incorporates a data backup unit configured within the BEOL structure, comprising ferroelectric memory elements and a control device, which allows for fast backup and restore operations without increasing the substrate footprint, thereby enhancing device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data backup unit is placed within the FEOL structure, then the data backup function is achieved, but the substrate footprint increases and device density decreases
Solution Approach 1:
The patent moves the data backup unit from the planar FEOL layer to the vertical BEOL structure, utilizing the third dimension (height/layer stacking) to accommodate the backup unit without expanding the substrate footprint. This dimensional transition allows concurrent operation of memory cells and backup units in different vertical layers.
Solution Approach 2:
The data backup unit is nested within the BEOL interconnect structure, which itself is stacked above the FEOL memory cell layer. This nested arrangement integrates the backup unit into the existing vertical architecture, maximizing space utilization and maintaining compact device footprint.
2Reliability
If the data backup unit is placed within the FEOL structure, then the data backup function is achieved, but device performance and speed are limited
Solution Approach 1:
By relocating the backup unit to the BEOL layer, the patent enables parallel processing paths where memory cell operations and data backup/restore operations occur simultaneously in different vertical layers, eliminating sequential bottlenecks and improving overall throughput and restoration speed.
Solution Approach 2:
The BEOL data backup unit can perform preliminary data preparation and buffering operations independently of the memory cell read/write operations, enabling faster data restoration by having backup data ready in advance in the vertically stacked backup structure.
3Quantity of substance
If vertical stacking of memory cells is implemented, then bit density increases, but device complexity increases
Solution Approach 1:
The BEOL structure serves multiple functions: it provides interconnect wiring for the memory cells, establishes vertical stacking for increased density, and hosts the data backup unit. This multi-functional use of the BEOL layer reduces overall device complexity by consolidating multiple requirements into a single structural solution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables rapid data restoration and concurrent memory cell operations, improving the overall speed and performance of the memory device while maintaining a compact footprint.
Implementation Method 1
The data backup unit comprises a first ferroelectric memory element and a second ferroelectric memory element
Data Source
AI summary
Various embodiments of the present application are directed towards a memory device including a memory cell. The memory cell includes a plurality of semiconductor devices disposed on a substrate. A lower inter-metal dielectric (IMD) structure overlies the semiconductor devices. A plurality of conductive vias and a plurality of conductive wires are disposed within the IMD structure and are electrically coupled to the semiconductor devices. A data backup unit overlies the plurality of conductive vias and wires. The data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer, a first memory gate structure, and a second memory gate structure. The first and second memory gate structures include an upper gate electrode over a ferroelectric layer. The first and second source/drain structures are directly electrically coupled to the semiconductor devices by way of the conductive vias and wires.