BEOL Thin-Film Ferroelectric Memory for Higher Density Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing device density due to limitations in scaling transistor dimensions, with existing technologies struggling to effectively integrate transistors from the front-end-of-line (FEOL) to the back-end-of-line (BEOL) for enhanced functionality and area utilization in integrated circuits.
Innovation Solution
The integration of ferroelectric memory devices using thin film transistors (TFTs) embedded in the BEOL, combined with field effect transistors, allows for the formation of a semiconductor structure where ferroelectric memory cells are connected to TFTs and field effect transistors, enabling programming and access through a series connection to achieve high device density and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then device density improves, but manufacturing precision and reliability deteriorate due to physical scaling limitations
Solution Approach 1:
The patent moves transistors from the traditional planar FEOL layer into the vertical BEOL dimension by embedding them within dielectric material layers. This dimensional transition allows transistors to be positioned in three-dimensional space above the substrate, effectively increasing device density without further scaling transistor dimensions in the planar direction. The transistors are integrated into interconnect levels, utilizing the vertical stacking capability of BEOL processing.
Solution Approach 2:
The patent separates transistor fabrication into distinct FEOL and BEOL stages. FEOL processes create the substrate and initial circuitry, while BEOL processes embed transistors within dielectric layers and form interconnects. This segmentation allows each stage to be optimized independently, with FEOL focusing on high-precision transistor fabrication and BEOL focusing on three-dimensional integration and routing.
2Area of stationary object
If transistors are moved from FEOL to BEOL to increase chip area availability, then chip area utilization improves, but device complexity increases due to integration challenges
Solution Approach 1:
Transistors are embedded within dielectric material layers in the vertical dimension, allowing them to occupy space above the substrate rather than competing for planar chip area. This vertical integration enables multiple transistor layers to be stacked, effectively multiplying the functional area available on a given chip footprint while maintaining standard planar routing methodologies.
Solution Approach 2:
The BEOL dielectric material layers serve multiple functions: they provide electrical isolation, mechanical support, and embedding medium for transistors, while also forming the interconnect structure. This multi-functionality reduces the need for separate structural elements, simplifying the overall integration process despite the increased three-dimensional complexity.
3Ease of manufacture
If thin film transistors are used in BEOL for low temperature processing, then ease of manufacture improves, but device complexity increases due to additional processing layers
Solution Approach 1:
The patent employs thin film transistors with oxide semiconductor channels that can be fabricated at low temperatures (below 400°C), compatible with BEOL processing constraints. This parameter change in fabrication temperature enables transistor integration without damaging previously formed FEOL structures, allowing standard BEOL dielectric and metal layering processes to be used without modification.
Solution Approach 2:
The transistor structure is replicated as thin film devices that can be deposited using standard BEOL deposition techniques. Rather than attempting to transfer or adapt thick-film or planar transistor structures, the invention uses thin film fabrication methods that naturally fit the layer-by-layer BEOL manufacturing paradigm, reducing process complexity despite additional layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density by allowing for high remnant polarization and coercive field in ferroelectric memory cells, providing stable and efficient memory storage with reduced lateral wiring distance between transistors and memory cells, thus overcoming the limitations of traditional scaling methods.
Implementation Method 1
a ferroelectric dielectric material layer, and a second electrode contacting a top surface of the ferroelectric dielectric material layer
Implementation Method 2
a gate electrode, a gate dielectric layer underlying the gate electrode, and a semiconductor channel overlying the gate dielectric layer
Data Source
AI summary
A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.