Semiconductor BEOL Interconnects Using Multiple Materials in FSAV Process
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Solution Overview
Problem
The challenge in semiconductor BEOL interconnects is the formation of uniform layer-to-layer interconnect structures, as device features shrink, requiring narrower vias, but existing materials like copper may have high resistivity, and using suitable materials for narrow interconnects can result in gaps or non-uniformities when applied to wider interconnects.
Innovation Solution
The method involves using multiple materials in a fully self-aligned via (FSAV) process, where different interconnect materials are deposited in specific regions of a patterned substrate, allowing for tailored interconnect structures by forming distinct interconnects in different regions with common layers, utilizing etch and plasma-assisted deposition systems to achieve uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If copper is used for device layer interconnects, then ease of manufacture is improved, but electrical conductivity deteriorates due to high resistivity in narrow vias
Solution Approach 1:
The patent applies local quality by using different interconnect materials for different regions: narrow vias use materials optimized for small dimensions (such as cobalt, tungsten, or ruthenium) while wider interconnects use materials optimized for lower resistivity (such as copper). This regional differentiation resolves the contradiction by allowing each region to have the material property best suited for its specific dimensional requirements, thereby maintaining both ease of manufacture and electrical conductivity.
Solution Approach 2:
The patent segments the interconnect structure into multiple material regions based on via width. The segmentation divides the interconnect network into narrow via regions and wide interconnect regions, each filled with appropriate materials. This segmentation allows the system to overcome the limitation of using a single material (copper) for all interconnects, resolving the contradiction between manufacturability and electrical performance.
2Reliability
If materials suitable for narrow interconnects are used, then electrical conductivity is improved, but manufacturing precision deteriorates due to gaps and non-uniformities in wider interconnects
Solution Approach 1:
By assigning different materials to different spatial regions (narrow vs. wide interconnects), the patent ensures that each region receives the material best suited for its dimensional characteristics. This local quality approach prevents the manufacturing defects (gaps and non-uniformities) that occur when inappropriate materials are used in wide interconnects, while simultaneously maintaining the electrical conductivity benefits in narrow vias.
Solution Approach 2:
The patent changes the material parameter based on the dimensional parameter (via width). By correlating material selection with interconnect width, the system optimizes both electrical conductivity and manufacturing precision. Narrow vias receive materials with properties suitable for small dimensions, while wide interconnects receive materials that fill uniformly and maintain precision.
3Area of moving object
If device footprint is decreased, then integration density is improved, but via width must be reduced which deteriorates material suitability
Solution Approach 1:
As device footprint decreases and via dimensions shrink, the patent applies local quality by using different materials in different regions. Narrow vias resulting from footprint reduction use materials specifically suited for small dimensions (cobalt, tungsten, ruthenium), while wider interconnect regions use copper. This resolves the material suitability issue that arises from footprint reduction.
Solution Approach 2:
The patent employs composite materials by combining multiple interconnect materials (copper, cobalt, tungsten, ruthenium) within the same device structure. This composite approach allows the system to accommodate reduced device footprint and varying via widths by selecting the appropriate material for each region, thereby maintaining reliability across all dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of uniform and efficient interconnects by using suitable materials for varying widths, reducing resistivity issues and ensuring consistent interconnect formation across different regions, thereby enhancing the reliability and performance of semiconductor BEOL interconnects.
Implementation Method 1
utilizing etch and plasma-assisted deposition systems to achieve uniformity
Data Source
AI summary
Embodiments of systems and methods for semiconductor back end of line (BEOL) interconnect using multiple materials in a fully self-aligned via (FSAV) process. In an embodiment, a method includes receiving a substrate with a patterned structure formed on a surface of the substrate. A method may also include depositing a first interconnect material in a first region of the patterned structure. Such methods may also include depositing a second interconnect material in a second region of the patterned structure, wherein the first interconnect material is different from the second interconnect material, and wherein the first region and the second region include a common layer of the patterned structures.