BEOL Interconnect Fuse Structure With Low-k ILD for Low-Voltage Programming
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Solution Overview
Problem
The scaling of features in integrated circuits, particularly in the 10 nanometer node and sub-10 nanometer range, is limited by variability in conventional fabrication processes, leading to challenges in lithographic processes, via spacing, and critical dimension control, which are not adequately addressed by existing technologies.
Innovation Solution
Implementing low-k inter-layer dielectric materials in the BEOL process, specifically at the M3 metal layer, to enhance fuse programming efficiency by reducing programming voltage and thermal dissipation, thereby improving power consumption and reducing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling to 10 nanometer node and below, then existing process methodologies can be maintained, but variability limits further extension and manufacturing precision deteriorates
Solution Approach 1:
The patent changes the physical and chemical parameters of the inter-layer dielectric material by using low-k materials with specific dielectric constants (2.0-3.5) and controlled thermal conductivity, enabling better control of programming voltage and thermal dissipation characteristics for improved manufacturing precision at sub-10nm nodes
Solution Approach 2:
The patent employs composite material structures combining low-k ILD materials with specific metal layer compositions (copper, cobalt, tungsten) and liner materials (tantalum, titanium), creating a multi-material system that optimizes both electrical and thermal properties for advanced node fabrication
2Quantity of substance
If feature size is reduced to increase device density, then capacity increases, but lithographic process constraints become overwhelming and manufacturing precision deteriorates
Solution Approach 1:
The patent addresses lithographic limitations by optimizing vertical stack structures and cross-sectional geometries of interconnect features, utilizing the third dimension to achieve higher density without proportionally reducing lateral feature sizes that are constrained by lithography
Solution Approach 2:
The patent applies different material properties and structural characteristics to specific regions of the interconnect stack, such as using low-k ILD specifically at certain metal layers (M3 and above) rather than uniformly across all layers, enabling localized optimization of electrical and thermal properties
3Ease of manufacture
If conventional ILD materials are used in BEOL process, then standard fabrication can be maintained, but fuse programming efficiency is insufficient and power consumption increases
Solution Approach 1:
The patent changes the thermal conductivity parameter of the ILD material by selecting low-k materials with reduced thermal conduction, which traps heat more effectively during fuse programming, reducing the energy required to achieve the necessary temperature for reliable fuse operation
Solution Approach 2:
The patent adopts the low-k ILD material approach from advanced logic device fabrication processes and applies it to interconnect and fuse structures, copying a proven methodology from one application to another to reduce programming power consumption
4Quantity of substance
If feature scaling continues to increase device capacity, then chip capacity increases, but fabrication process variability worsens and new methodologies are required
Solution Approach 1:
The patent modifies material parameters (dielectric constant, thermal conductivity) to create a more controllable fabrication environment that is less sensitive to process variability, enabling continued scaling while maintaining manufacturing control through physics-based optimization rather than relying solely on tighter process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of low-k ILD materials at the M3 metal layer enables efficient fuse programming at lower voltages (1.2V), reducing power consumption and costs while maintaining reliability and density, without additional circuitry, thus enhancing integrated circuit performance.
Implementation Method 1
enhance fuse programming efficiency by reducing programming voltage and thermal dissipation
Data Source
AI summary
Back-end-of-line (BEOL) interconnect fuses are described. In an example, an integrated circuit structure includes a first dielectric layer having first conductive lines therein. A second dielectric layer is over the first dielectric layer and has first conductive vias and second conductive lines therein. One of the second conductive lines is a fuse element. A third dielectric layer is over the second dielectric layer and has second conductive vias and third conductive lines therein. The second dielectric layer has a lower dielectric constant than the first dielectric layer and than the third dielectric layer, or the second dielectric layer has a lower thermal conductivity than the first dielectric layer and than the third dielectric layer, or both.