BEOL GAA Nanosheet Memory Structure for Leakage and Ion Limits
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Solution Overview
Problem
Existing BEOL memory devices with planar channel structures suffer from high current leakage between neighboring cells and insufficient Ion due to potential differences between source and drain, even when the gate is turned off, and small effective channel width.
Innovation Solution
The implementation of a three-dimensional gate-all-around (GAA) memory device with interleaved nanosheet channel layers, where the channel layers are wrapped by a gate structure, enhancing gate control and increasing the effective channel width, thereby mitigating leakage and improving Ion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar channel structure is used in BEOL memory devices, then the device structure is simple and easy to manufacture, but current leakage between neighboring cells increases and Ion performance becomes insufficient
Solution Approach 1:
The patent transitions from a two-dimensional planar channel structure to a three-dimensional gate-all-around nanosheet structure. The channel layers are stacked vertically and completely surrounded by the gate structure, adding spatial dimensionality to achieve superior gate control and eliminate leakage paths between adjacent cells while maintaining manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The gate structure completely surrounds and encloses the nanosheet channel layers in a nested configuration. The gate wraps around the channel from all sides, creating a nested doll-like structure where the gate contains the channel, enabling 360-degree control of the channel and preventing leakage without requiring complex lateral isolation structures.
2Device complexity
If a planar channel structure is used in BEOL memory devices, then the device structure is simple, but the effective channel width is small leading to insufficient Ion
Solution Approach 1:
The patent increases the effective channel width by stacking multiple nanosheet channels vertically in the third dimension. Instead of expanding the channel width laterally in the planar direction, the invention stacks multiple thin channel layers one on top of another, each surrounded by the gate, thereby multiplying the effective channel width without increasing lateral device footprint or complexity.
Solution Approach 2:
The channel is segmented into multiple discrete nanosheet layers stacked vertically. Each nanosheet acts as an independent conducting path controlled by the surrounding gate. This segmentation allows the total effective channel width to be the sum of all individual nanosheet widths, achieving high Ion performance while maintaining compact lateral dimensions and manageable device complexity.
3Use of energy by moving object
If the gate is turned off in planar channel structures, then power consumption is reduced, but potential differences between source and drain cause current leakage
Solution Approach 1:
The gate completely surrounds the channel in a nested configuration, providing 360-degree control. When the gate is turned off, the enclosed structure maintains electrostatic control over the entire channel perimeter, preventing leakage currents that would otherwise flow between source and drain even when the gate voltage is zero, thereby enabling true power-off state with minimal leakage.
Solution Approach 2:
By moving to a 3D gate-all-around structure, the gate controls the channel from all spatial directions including top, bottom, and sides. This multi-dimensional control creates additional electrostatic potential barriers when the gate is off, preventing leakage paths that exist in planar structures where gate control is limited to one dimension, thus reducing leakage without increasing power consumption.
Data Source
AI summary
A memory device includes a semiconductor substrate. The memory device includes a stack of channel layers over the semiconductor substrate, each channel layer including an oxide material. The memory device includes a word line structure interleaved with the stack of channel layers. The memory device includes a source feature and a drain feature on both sides of the stack of channel layers.