BEOL Grating Spacer Patterning for EUV Overlay Margin
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Solution Overview
Problem
As semiconductor devices scale to smaller critical dimensions, edge placement error margins decrease, leading to defects such as unwanted vias and shorts in the BEOL stack, which are challenging to manage with existing grating-based overlay margins.
Innovation Solution
The introduction of a conformal spacer layer that is etch selective to the grating, allowing for increased edge placement error margins by expanding the width of the grating lines and enabling longer etching durations compatible with high-volume manufacturing tools, while minimizing damage to the underlying structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gratings are used to provide increased overlay margins, then edge placement error margins are improved, but as critical dimensions scale down, the widths of the gratings decrease and the margins for edge placement error continue to decrease
Solution Approach 1:
The patent transitions from relying solely on grating width (one dimension) to utilizing the vertical dimension by forming a conformal spacer layer over the grating. This spacer layer provides additional overlay margin in the vertical direction, compensating for the reduction in horizontal grating width as critical dimensions scale down.
Solution Approach 2:
The conformal spacer layer acts as an intermediary element between the grating and the subsequent patterning layers. It provides a physical buffer that increases the effective overlay margin, allowing the grating to maintain its function as an alignment reference even when its width is reduced for scaling.
2Manufacturing precision
If etching is used to transfer the grating into the ILD, then the grating pattern is transferred, but damage may occur to the grating or underlying structures during the etching process
Solution Approach 1:
The conformal spacer layer serves as a protective intermediary during the etching process. It is positioned between the etch chemistry and the grating structure, absorbing or mitigating the harmful effects of the etchant and preventing direct damage to the grating and underlying ILD structures.
Solution Approach 2:
The spacer layer is formed beforehand to provide a cushioning protective layer that prevents etching damage before the damage can occur to critical structures. This pre-positioned protection allows the etching process to proceed with reduced risk to the grating and underlying layers.
3Ease of manufacture
If conventional patterning is used, then the process is simple, but edge placement errors generate defects such as unwanted vias and shorts in the BEOL stack
Solution Approach 1:
The conformal spacer layer is formed as a preliminary structure before the final patterning step. This pre-formed spacer provides built-in overlay margin that compensates for alignment errors, allowing the use of conventional patterning processes while achieving improved reliability and reduced defect rates.
Solution Approach 2:
The invention changes the geometric parameters of the grating structure by adding the vertical spacer dimension. This parameter change increases the effective overlay margin without requiring changes to the fundamental patterning process, thus maintaining ease of manufacture while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively increases edge placement error margins, enhances manufacturability, and reduces defects by allowing for more precise control over the etching process, accommodating smaller critical dimensions without damaging the grating or interlayer dielectric.
Implementation Method 1
forming a spacer over the grating, wherein the spacer is etch selective to the grating
Implementation Method 2
transferred the grating into the ILD with an etching process
Implementation Method 3
etch-selective materials and processes, such as a sacrificial layer and biased dry etching
Data Source
AI summary
Embodiments disclosed herein include methods of patterning a back end of line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.