BEOL IGZO 2T Gain Cell Memory for Dense Low-Leakage DRAM
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Solution Overview
Problem
High-density memory technologies like 1T-1C eDRAM for multi-core processors increase manufacturing complexity and costs due to complex CMOS processes, particularly with silicon transistors and capacitors, which impact yield and total system cost.
Innovation Solution
Integration of c-axis-aligned crystalline indium-gallium-zinc-oxide (CAAC-IGZO) transistors in the backend metal process stack, allowing for lower temperature processing and reduced complexity, combined with IGZO transistors in separate layers for 2T gain cell memory structures, which simplifies the manufacturing process and enhances memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1T-1C eDRAM is integrated into multi-core processors, then memory density increases, but manufacturing complexity and process costs increase
Solution Approach 1:
The patent extracts the transistor fabrication process from the complex front-end CMOS process stack and relocates it to the backend metal process stack. Specifically, IGZO transistors are formed in interlayer dielectric layers after the main CMOS processing is complete, separating the memory cell transistor formation from the processor transistor fabrication. This extraction eliminates the need for complex dual-process integration while maintaining high memory density.
Solution Approach 2:
The patent transitions from planar transistor fabrication to vertical stacking by forming transistors within three-dimensional interlayer dielectric structures. The IGZO transistors are created by depositing conductive layers and forming vertical channels through multiple dielectric layers, enabling memory cells to be stacked above processor circuits in the vertical dimension rather than competing for lateral space.
2Quantity of substance
If silicon transistors and capacitors are used in high-density memory, then memory capacity increases, but yield decreases due to process complexity
Solution Approach 1:
The patent replaces expensive, complex silicon-based transistor fabrication with a simpler, more robust IGZO transistor formation process that can be performed using standard backend metal deposition equipment. The IGZO transistors use abundant materials and straightforward deposition techniques, making the process more reliable and less prone to defects while achieving the required memory capacity.
3Reliability
If complex CMOS processes are used for memory fabrication, then memory performance improves, but total system cost increases
Solution Approach 1:
The patent creates a universal backend process that can fabricate both processor interconnects and memory cell transistors using the same deposition and patterning equipment. The IGZO transistor formation process is integrated into the standard backend metal stack used for processor interconnects, eliminating the need for separate memory-specific fabrication lines and reducing overall manufacturing costs while maintaining performance.
Data Source
AI summary
An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.