BEOL Inductor Capacitor Vertical Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional BEOL wiring structures inefficiently use chip area due to separate areas for on-chip inductors and capacitors, leading to reduced space for active device connections and suboptimal substrate isolation.
Innovation Solution
A vertically stacked arrangement of on-chip capacitors and inductors in the BEOL wiring structure, where the capacitor acts as a Faraday shield, conserving area and eliminating the need for a discrete Faraday shield, and a tunable LC resonator is achieved by selectively coupling a floating electrode with the capacitor electrodes during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate areas are used for on-chip inductors and capacitors in conventional BEOL wiring structures, then each passive device can be independently fabricated, but the chip area usage becomes inefficient and space for active device connections is reduced
Solution Approach 1:
The patent merges the inductor and capacitor into a single integrated passive device structure where the capacitor is formed within the same planar region as the inductor. The capacitor plates are positioned between the inductor windings and the substrate, allowing both passive components to occupy the same chip area rather than requiring separate dedicated regions for each device.
Solution Approach 2:
The integrated structure serves multiple functions simultaneously: the capacitor plates provide capacitance function, the inductor windings provide inductance function, and the capacitor plates also serve as a Faraday shield for substrate isolation. This multi-functionality eliminates the need for separate Faraday shield structures and maximizes area efficiency.
2Object-affected harmful factors
If a discrete Faraday shield is added to the BEOL wiring structure for substrate isolation, then substrate isolation is improved, but the device complexity and area usage increase
Solution Approach 1:
The capacitor plates are designed to perform dual functions: providing the necessary capacitance for the passive device and simultaneously serving as a Faraday shield to isolate the inductor from the substrate. This eliminates the need for a separate discrete Faraday shield structure, reducing overall device complexity while maintaining effective substrate isolation.
Solution Approach 2:
The Faraday shield function is merged with the capacitor structure by positioning the capacitor plates between the inductor windings and the substrate. This integration means the same conductive elements that store electrical energy also provide electromagnetic shielding, simplifying the overall device architecture.
3Ease of manufacture
If completely separate areas are allocated for on-chip inductors and capacitors, then fabrication processes remain simple, but the area available for active device connections is reduced
Solution Approach 1:
The inductor and capacitor are merged into a single integrated structure occupying the same planar area, which frees up chip real estate for active device interconnections. The integration is achieved through coordinated patterning of conductive layers that form both passive components within a unified geometric footprint.
Solution Approach 2:
The patent utilizes the vertical dimension by positioning capacitor plates in an intermediate layer between the inductor windings and the substrate. This three-dimensional arrangement allows both passive components to coexist in the same planar footprint while maintaining their electrical functions, thereby maximizing the area available for active device connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the quality factor of the inductor, optimizes chip area usage, and allows for compact, efficient integration of passive devices, thereby improving the performance and efficiency of RFICs by enabling more effective substrate isolation and tunable resonance frequencies.
Implementation Method 1
conventional BEOL wiring structures may rely on a Faraday shield at the first metal (M1) level to optimize substrate isolation of on-chip inductors
Implementation Method 2
forming a plurality of second conductive features in the at least one second metallization level that define an on-chip capacitor, which is positioned laterally in the at least one second metallization level such that the on-chip capacitor is in substantially vertical alignment with the on-chip inductor
Data Source
AI summary
Methods for fabricating a back-end-of-line (BEOL) wiring structure that includes an on-chip inductor and an on-chip capacitor, as well as methods for tuning and fabricating a resonator that includes the on-chip inductor and on-chip capacitor. The fabrication methods generally include forming the on-chip capacitor and on-chip inductor in different metallization levels of the BEOL wiring structure and laterally positioned to be substantially vertical alignment. The on-chip capacitor may serve as a Faraday shield for the on-chip inductor. Optionally, a Faraday shield may be fabricated either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the directly-connected electrodes of the on-chip capacitor for tuning, during circuit operation, a resonance frequency of an LC resonator that further includes the on-chip inductor.