BEOL Inductor Capacitor Vertical Stacking
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Solution Overview
Problem
Conventional back-end-of-line (BEOL) wiring structures inefficiently use chip area by separating on-chip inductors and capacitors, leading to reduced space for active device connections and suboptimal performance due to parasitic capacitance and resistance.
Innovation Solution
A vertically stacked arrangement of on-chip capacitors and inductors in the BEOL wiring structure, where the capacitor is positioned between the inductor and the substrate, allowing it to function as a Faraday shield and optimizing substrate isolation, thus conserving chip area and enhancing inductor quality factor Q.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip inductors and capacitors are completely separated in the BEOL wiring structure, then each passive device can be optimized independently, but the chip area usage becomes inefficient and the space for active device connections is reduced
Solution Approach 1:
The patent combines the capacitor and inductor into a single integrated passive device structure, where the capacitor is formed in one metallization level and the inductor in another, with vertical alignment between them. This merging approach maintains independent optimization of each component while achieving compact area utilization through shared structural elements and vertical stacking.
Solution Approach 2:
The invention transitions from a planar layout to a three-dimensional vertically stacked configuration. The capacitor and inductor are positioned in different metallization levels with vertical alignment, utilizing the vertical dimension to reduce the lateral footprint while maintaining independent functionality of each component.
2Ease of manufacture
If conventional separate areas are used for on-chip inductors and capacitors, then each device can be designed independently, but the area available for conductive paths connecting active devices is reduced
Solution Approach 1:
The integrated passive device merges the capacitor and inductor designs into a unified structure that shares common structural elements and alignment references, enabling independent design of each component while maintaining compact integration that preserves space for interconnect paths.
3Reliability
If a discrete Faraday shield is added to optimize substrate isolation of on-chip inductors, then the quality factor Q improves, but the device complexity and area usage increase
Solution Approach 1:
The capacitor structure is designed to serve dual functions: its primary function as a capacitive element and a secondary function as a Faraday shield for substrate isolation of the inductor. This multi-functionality eliminates the need for a separate discrete Faraday shield, reducing device complexity while maintaining effective substrate isolation.
Solution Approach 2:
The capacitor structure provides substrate isolation shielding for the inductor, effectively having the capacitor 'self-serve' an additional protective function. This self-service approach reduces the need for separate shielding components and simplifies the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a compact form factor for passive devices, reducing energy losses and increasing the quality factor Q of the on-chip inductor, while also eliminating the need for a discrete Faraday shield, thereby improving the efficiency of chip area usage and performance.
Implementation Method 1
the on-chip capacitor is positioned laterally within the at least one second metallization level such that the on-chip capacitor is in a substantially vertical alignment with the on-chip inductor in the at least one first metallization level
Data Source
AI summary
Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.