BEOL Interconnect Isolation Trenches With Post-Cap Air Gaps
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Solution Overview
Problem
Traditional patterning techniques for semiconductor interconnects, such as lithography etch and self-aligned double patterning, are limited in reducing the distance between metal lines and vias due to mask design constraints, which hampers the miniaturization of integrated circuits and affects isolation between elements.
Innovation Solution
The method involves forming cavities in metal lines and vias after metallization, using chemical mechanical polishing and post cap liners to remove portions of the metal lines and vias, allowing for improved spacing and isolation by filling the cavities with dielectric materials and creating air gaps, thereby reducing the footprint and enhancing optical proximity correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional lithography etch or self-aligned double patterning is used to pattern metal lines and vias, then the manufacturing process is well-established and reliable, but the minimum distance between metal lines and vias cannot be reduced further due to mask design constraints
Solution Approach 1:
The patent segments the patterning process into two independent stages: first forming metal lines and vias with conventional lithography, then separately forming isolation trenches between them. This segmentation allows each stage to be optimized independently, enabling reduced spacing without compromising the alignment precision achieved by traditional mask-based patterning.
Solution Approach 2:
The patent performs preliminary formation of metal interconnect structures using established lithography techniques before introducing the subtractive etching step. This preliminary action establishes the metal line and via positions with high precision, and subsequent isolation trench formation does not interfere with this already-established pattern alignment.
2Area of stationary object
If metal lines and vias are placed closer together to reduce footprint, then the integrated circuit miniaturization is improved, but the isolation between metal lines and vias deteriorates
Solution Approach 1:
The patent extracts the isolation function from the metal patterning process itself. After metal lines and vias are formed, the method selectively removes (extracts) dielectric material to create isolation trenches between adjacent metal structures. This extraction of isolation regions enables close spacing of metal interconnects while maintaining electrical and thermal isolation through the trench structures filled with insulating material.
Solution Approach 2:
The patent applies local quality by creating isolation trenches only in specific regions between metal lines and vias, rather than uniformly across the entire structure. The subtractive etching process selectively removes dielectric material at locations where isolation is needed, preserving the metal interconnect continuity while providing localized electrical and thermal isolation where required.
3Length of moving object
If subtractive etching is used to form isolation trenches between metal lines and vias, then the isolation and spacing are improved, but the process complexity increases
Solution Approach 1:
The patent inverts the conventional approach by forming metal interconnect structures first, then creating isolation trenches by removing dielectric material between them. This inversion of the traditional sequence (where isolation is formed before metal patterning) allows the use of simple subtractive etching processes to achieve precise isolation, reducing overall process complexity compared to attempting to form both metal patterns and isolation features in a single lithography step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reduced dimensions and improved isolation between metal lines and vias, enhancing thermal and electrical isolation and allowing for more compact and efficient semiconductor structures.
Implementation Method 1
using chemical mechanical polishing and post cap liners to remove portions of the metal lines and vias
Data Source
AI summary
A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.