BEOL Interconnect Barrier Layout for Lower Resistance and Coupling
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Solution Overview
Problem
As semiconductor industry advances, the increasing aspect ratio of conductive features in back-end-of-line (BEOL) interconnect structures leads to higher electrical resistivity, necessitating improved interconnect structures to maintain performance and functionality.
Innovation Solution
The implementation of separate metal barrier layers and a dielectric material with a capping layer, along with a blocking layer and metal oxide layer, to reduce contact resistance and capacitive coupling between conductive features, thereby minimizing time-dependent dielectric breakdown (TDDB) failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of conductive features is increased to achieve higher density, then the density of elements increases, but electrical resistivity increases
Solution Approach 1:
The conductive feature is segmented into multiple portions along its length, with separate barrier layers formed on each portion. This segmentation allows for optimized barrier coverage at critical interfaces while maintaining overall conductivity, addressing the increased resistivity issue that arises from higher aspect ratios in dense interconnect structures.
Solution Approach 2:
Different barrier layer configurations are applied to different portions of the conductive feature based on local requirements. Specifically, first and second barrier layers are formed on adjacent portions, with dielectric material disposed between them, providing localized quality enhancement at interfaces where contact resistance and capacitive coupling are most problematic.
2Reliability
If separate barrier layers and dielectric material are added to reduce contact resistance and capacitive coupling, then reliability improves, but device complexity increases
Solution Approach 1:
Multiple functional layers (barrier layers, dielectric material, capping layers) are merged into an integrated interconnect structure that simultaneously addresses contact resistance, capacitive coupling, and TDDB prevention. This combining approach achieves multiple reliability improvements through a unified structure rather than separate components.
Solution Approach 2:
Dielectric material is introduced as an intermediary substance between adjacent portions of conductive features. This intermediate layer acts as a mediator that reduces capacitive coupling and prevents direct interaction between neighboring conductors, thereby improving reliability without requiring direct modification of the conductive materials themselves.
3Object-generated harmful factors
If dielectric material is disposed between barrier layers to reduce capacitive coupling, then line-to-line leakage decreases, but manufacturing precision requirements increase
Solution Approach 1:
Barrier layers are formed on adjacent portions of conductive features before the dielectric material is deposited between them. This preliminary action establishes defined boundaries and surfaces that guide subsequent dielectric material placement, reducing the precision requirements for the dielectric deposition process while ensuring proper positioning.
Solution Approach 2:
The dielectric material is specifically disposed in the region between the first and second barrier layers where capacitive coupling and line-to-line leakage are most problematic. This localized placement strategy focuses the dielectric's beneficial effects precisely where needed, rather than requiring uniform coverage across the entire interconnect structure.
Data Source
AI summary
An interconnect structure, along with methods of forming such, are described. The structure includes a dielectric layer, a conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent the first portion. The structure also includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a dielectric material disposed between and in contact with the first and second barrier layers, wherein a bottom surface of the second barrier layer and a bottom surface of the dielectric material are substantially co-planar.