BEOL Interconnects for Multi-Chip IC Packaging
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Solution Overview
Problem
The challenge in integrated circuit (IC) chip fabrication lies in interconnecting multiple IC chips, particularly due to impenetrable structures like crack-stops, which complicate packaging and assembly, limiting minimum package size, the number of interconnected chips, and communication quality between IC chips, as well as compatibility issues with chips of different sizes.
Innovation Solution
The solution involves a packaging substrate with specific bond pad arrays and an interconnect structure that allows for the electrical connection of both operable and inoperable IC chips, enabling interconnects between IC chips during the back-end-of-line (BEOL) processing, rather than during packaging, using interchangeable masks to form either single or multiple interconnected IC chips from the same initial structure, thereby reducing fabrication complexity and improving communication bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If packaging interconnects are used to connect IC chips after fabrication, then IC chips can be interconnected to form multi-chip modules, but the minimum package size is limited and the number of interconnected chips is limited
Solution Approach 1:
The patent transitions from planar packaging interconnection to three-dimensional vertical interconnection by forming through-substrate vias that penetrate the substrate thickness direction. This allows IC chips to be stacked vertically and interconnected through the substrate, enabling more chips to be interconnected within a smaller footprint area by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The patent divides the substrate into multiple regions with separate through-substrate via structures, allowing independent interconnection of multiple IC chips. Each IC chip can be connected to the substrate through dedicated via regions, enabling modular expansion of the number of interconnected chips without proportionally increasing the overall package size.
2Reliability
If packaging interconnects are used to connect IC chips, then IC chips can be interconnected, but the quality of communication between IC chips is limited
Solution Approach 1:
The patent performs interconnection formation during the back-end-of-line (BEOL) fabrication process before final packaging, rather than during subsequent packaging operations. Through-substrate vias and interconnect structures are formed while the substrate is still in the fabrication wafer state, allowing precise alignment and integration with IC chip bond pads before dicing and packaging, thereby improving communication quality and reducing assembly complexity.
3Reliability
If crack-stop structures are used to protect IC components, then IC chips are protected, but interconnection between IC chips becomes difficult
Solution Approach 1:
The patent segments the crack-stop structures by introducing openings or discontinuities in the crack-stop layers at specific locations where through-substrate vias need to pass through. This allows the crack-stop structures to maintain their protective function in most areas while permitting via formation and interconnection in designated regions, resolving the conflict between protection and interconnectability.
Solution Approach 2:
The patent extracts or removes portions of the crack-stop structures to create via openings, allowing interconnect structures to penetrate the substrate. By selectively removing crack-stop material only where vias are needed, the patent enables interconnection while preserving the protective function of crack-stops in all other areas.
Data Source
AI summary
An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.