Self-Aligned BEOL Interconnect Fill for Overlay Margin and Low-k Voids
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Solution Overview
Problem
Photolithography misalignment in Back End Of the Line (BEOL) metallization leads to patterning defects such as line and vertical interconnect access discontinuities, affecting product reliability and wafer yield due to the narrow alignment window provided by hard mask (HM) usage.
Innovation Solution
A BEOL interconnect fabrication method employing self-aligned patterning and multi-metal gap fill processes, eliminating the need for a hard mask and incorporating a dielectric layer with naturally occurring voids to reduce dielectric constant and increase overlay alignment margin, using conductive materials like graphene and metal oxide layers for protection and etch stopping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hard mask is used for patterning, then patterning precision is improved, but device complexity increases and alignment window narrows
Solution Approach 1:
The patent removes the hard mask layer from the conventional patterning process, extracting this intermediate component to simplify the overall structure. The self-aligned spacer directly defines the via opening without requiring a hard mask, thereby reducing process complexity while maintaining patterning precision through the spacer's geometric definition
Solution Approach 2:
The spacer structure serves multiple functions: it acts as both the patterning definition element and the etch mask, eliminating the need for separate hard mask layer. This multi-functionality reduces the number of process steps and materials required, directly addressing the device complexity issue while preserving manufacturing precision
2Manufacturing precision
If hard mask is used for patterning, then patterning precision is improved, but overlay alignment window narrows
Solution Approach 1:
The spacer structure is self-aligned to the mandrel, automatically defining the via opening position without requiring separate alignment steps. This self-service mechanism eliminates alignment errors between different photolithography steps, significantly improving overlay alignment margin while maintaining patterning precision through the spacer's geometric definition
Solution Approach 2:
The mandrel is formed first as a reference structure, and the spacer is subsequently formed aligned to it. This preliminary action establishes a fixed reference point that guides subsequent via opening formation, ensuring consistent alignment and expanding the overlay alignment window by eliminating cumulative alignment errors
3Reliability
If dielectric layer with voids is used, then dielectric constant is reduced, but manufacturing complexity increases
Solution Approach 1:
The dielectric layer incorporates voids or porous structures to reduce the effective dielectric constant, which improves signal integrity by reducing parasitic capacitance. The voids are formed through controlled deposition or etching processes that create a porous network within the dielectric material, achieving the desired electrical performance while managing manufacturing complexity through established porous material fabrication techniques
Data Source
AI summary
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.