BEOL Interconnects Using Selective Spacer Etching

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Solution Overview

Problem

Current back-end-of-line (BEOL) interconnect fabrication in semiconductor devices faces challenges in achieving efficient multi-patterning of interconnects due to the need for hierarchical wiring management and material selection for reduced costs, with existing methods lacking in defining the right material set for effective patterning and etching processes.

Innovation Solution

A semiconductor structure comprising mandrel lines and non-mandrel lines in an alternating pattern with spacers disposed between them, where the spacers have an etch rate greater than the mandrel and non-mandrel lines, allowing for selective removal and enabling efficient formation of BEOL interconnects through a process involving photolithography, etching, and wet etch processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If spacers with etch rate greater than mandrel and non-mandrel lines are used, then selective removal of spacers is enabled, but the etching process complexity increases

Engineering Contradiction:
Improveselective spacer removalVSAvoidetching process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different etch rate characteristics to different materials in the structure. The spacer material is specifically selected or engineered to have an etch rate greater than both the mandrel lines and non-mandrel lines, enabling selective removal of spacers while preserving the interconnect lines during the etching process.

Inventive Principle:
Principle #3Local quality

2Productivity

If hierarchical wiring management is implemented, then component density is increased, but the fabrication process complexity increases

Engineering Contradiction:
Improvecomponent densityVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements segmentation by dividing the interconnect structure into distinct functional segments: mandrel lines for initial patterning, spacers for defining additional features, and non-mandrel lines for final interconnect formation. This segmented approach enables hierarchical wiring management that increases component density while maintaining a systematic fabrication process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by forming the mandrel lines and spacers before creating the final non-mandrel interconnect lines. The mandrel lines serve as preliminary structures that guide the formation of spacers, which in turn define the positions of the final interconnect lines, enabling efficient multi-patterning and hierarchical wiring management.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If alternating pattern of mandrel and non-mandrel lines is formed, then interconnect efficiency is improved, but the patterning process complexity increases

Engineering Contradiction:
Improveinterconnect efficiencyVSAvoidpatterning process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple patterning functions into a unified process flow. The alternating pattern of mandrel and non-mandrel lines is achieved by combining the formation of mandrel lines, spacer deposition, and non-mandrel line creation in an integrated sequence, where each step builds upon the previous one to efficiently create the final interconnect pattern.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach facilitates the formation of stable and efficient BEOL interconnects by enabling high selectivity in spacer removal, maintaining the integrity of mandrel and non-mandrel lines, and supporting increased component density in integrated circuits through hierarchical wiring management.

Implementation Method 1

An etch rate of the spacers is greater than an etch rate of the mandrel lines and the non-mandrel lines

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

allowing for selective removal and enabling efficient formation of BEOL interconnects through a process involving photolithography, etching, and wet etch processes

Methodology Applied
Scientific EffectWet etch:

Data Source

PatentUS11682558B2Fabrication of back-end-of-line interconnects
Publication Date: 2023.06.20 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11682558B2 patent drawing
  • US11682558B2 patent drawing
  • US11682558B2 patent drawing

AI summary

A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.