BEOL High-Resistance Interconnect Layout for Uniform Via Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down devices while maintaining uniform contact resistance and efficient design area utilization, particularly in the Back End Of the Line (BEOL) area of integrated circuits, where high resistance layers are needed to optimize circuit performance.
Innovation Solution
Incorporating a high resistance layer in the BEOL area between metallization layers, using dielectric layers of similar thickness and materials as etch stops to control the bottom surface areas of conductive vias, which allows for uniform contact resistance and reduces analog circuit design area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high resistance layer is placed below metallization layers in MEOL or FEOL area, then device performance is improved, but analog circuit design area increases by around 5%
Solution Approach 1:
The patent moves the high resistance layer from the traditional below-metallization position (MEOL/FEOL) to an above-metallization position (BEOL), utilizing the vertical dimension to resolve the contradiction. This dimensional repositioning allows the high resistance layer to coexist with metallization layers without occupying additional horizontal design area, thereby maintaining device performance while reducing analog circuit design area by 5%.
2Ease of manufacture
If etch stops are not properly controlled, then manufacturing process is simpler, but contact resistance uniformity deteriorates
Solution Approach 1:
The patent applies homogeneity by making the dielectric layers above and below the high resistance layer substantially similar in thickness and material composition. This symmetry ensures that etch stops function uniformly during fabrication, producing consistent bottom surface areas for conductive vias and thereby achieving uniform contact resistance across the device while maintaining ease of manufacture.
3Productivity
If device geometry is scaled down, then production efficiency increases and costs decrease, but maintaining uniform contact resistance becomes more difficult
Solution Approach 1:
The patent changes the spatial parameter of the high resistance layer from below-metallization to above-metallization positioning in the BEOL area. This parameter change allows the structure to accommodate scaled-down device geometries while maintaining uniform contact resistance, as the high resistance layer can be precisely controlled in the vertical dimension without interfering with the scaled horizontal dimensions of the devices.
Data Source
AI summary
A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.