BEOL Interconnect Etch Layout for Bowing-Free Via and Trench Profiles
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Solution Overview
Problem
Existing BEOL dual damascene etch processes face challenges with high aspect ratio vias leading to via bowing, misalignment issues, varying via depths, and tapered trench profiles, resulting in increased signal interference, resistance, and fabrication costs.
Innovation Solution
A novel BEOL interconnect process involving separate via and trench etch processes, using etch stop layers to control via and trench profiles, filling vias with sacrificial materials, and employing a middle ESL to land on the trench, reducing aspect ratios and simplifying etch selectivity requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional dual damascene etch process is used to form vias and trenches, then interconnect structures can be formed, but high aspect ratio vias cause via bowing and misalignment issues
Solution Approach 1:
The patent divides the via formation process into multiple etch steps with intermediate planarization. The via is formed in stages rather than as a single deep etch, breaking the complex high aspect ratio via formation into manageable segments that can be controlled more precisely at each step.
Solution Approach 2:
The patent performs preliminary planarization steps before completing via etching. By planarizing the surface intermediate to via formation, the process prepares the structure in advance to receive subsequent etching steps, ensuring better alignment and reducing via bowing by controlling the etch front.
2Reliability
If deep vias are etched to reach lower interconnect layers, then electrical continuity is achieved, but via depths vary and misalignment occurs
Solution Approach 1:
The patent incorporates intermediate inspection and planarization steps that provide feedback on via formation progress. By measuring and planarizing at intermediate stages, the process can detect and correct depth variations before final via completion, ensuring uniform via depths and proper alignment.
Solution Approach 2:
The patent performs preliminary etching to create via openings, then planarizes before completing the etch to the final depth. This staged approach with intermediate planarization ensures that via depths are uniform and alignment is maintained throughout the etching process.
3Ease of manufacture
If trenches are etched with high aspect ratios, then interconnect structures are formed, but tapered trench profiles increase resistance
Solution Approach 1:
The patent segments the trench etching process into multiple steps with intermediate planarization. By breaking the deep trench etch into manageable segments, the process maintains better trench profile control at each step, reducing tapering that would otherwise occur in a single deep etch.
Solution Approach 2:
The patent performs preliminary trench etching to establish the trench path and depth, then planarizes before completing the etch. This preliminary action creates a controlled foundation that prevents excessive trench tapering and ensures straighter trench profiles with lower resistance.
4Manufacturing precision
If strict alignment and etch selectivity are enforced to achieve good via and trench profiles, then manufacturing precision improves, but fabrication complexity and costs increase
Solution Approach 1:
The patent performs preliminary etching to create via openings and establish trench paths, then planarizes before completing the etch to final dimensions. This preliminary action with intermediate planarization relaxes the strictness of final alignment and selectivity requirements by pre-establishing the structure geometry.
Solution Approach 2:
The patent segments the etch process into multiple steps with intermediate planarization, which distributes the precision requirements across multiple easier-to-control steps rather than demanding extreme precision in a single step, thereby reducing overall fabrication complexity.
Data Source
AI summary
A method during a back-end-of-line (BEOL) process for making a semiconductor device includes forming a first dielectric layer over a metal layer disposed on a substrate and a first etch stop layer over the first dielectric layer, forming a via that extends through the first etch stop layer and the first dielectric layer, filling the via with a sacrificial material, forming a second dielectric layer over the first etch stop layer and the via that is filled with the sacrificial material, and performing a first etch process to form a trench in the second dielectric layer, the trench being landed on the first etch stop layer and aligned with the via, the sacrificial material filled in the via being removed during the first etch process.