BEOL Interconnection Structure with Air Gaps and Direct Contact
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Solution Overview
Problem
As semiconductor technology advances, the increasing aspect ratio of conductive features in back-end-of-line (BEOL) interconnection structures leads to higher electrical resistivity and resistive-capacitive (RC) delays, necessitating improved methods for forming interconnection structures.
Innovation Solution
The implementation of a method that forms conductive features without a barrier or liner layer, allowing direct contact and reducing contact resistance, while incorporating air gaps in dielectric layers to lower capacitance and RC delay, is achieved through specific deposition processes and the use of blocking layers to selectively deposit barrier and liner materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier and liner layers are formed on conductive features, then electrical resistance at interfaces is reduced, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The patent removes the barrier and liner layers from the conductive feature interfaces, eliminating the harmful contact resistance caused by these intermediate layers while maintaining electrical connection through direct contact between conductive features
Solution Approach 2:
Instead of adding barrier and liner layers to reduce interface resistance as in conventional approaches, the patent inverts the approach by removing these layers entirely and using air gaps to achieve lower contact resistance and improved electrical performance
2Ease of manufacture
If dielectric layers are formed without air gaps, then manufacturing process is simplified, but capacitance increases and RC delay worsens
Solution Approach 1:
The patent introduces air gaps (porous structures) within the dielectric layers, creating regions of low dielectric constant that reduce capacitance between conductive features while maintaining the overall structural integrity and simplifying the manufacturing process
3Ease of manufacture
If conventional interconnection structures are used, then manufacturing is straightforward, but RC delay increases and signal routing performance deteriorates
Solution Approach 1:
The patent changes the dielectric constant parameter by introducing air gaps with effectively zero dielectric constant, thereby reducing capacitance and RC delay while maintaining manufacturing feasibility through modified deposition processes that create the desired porous structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and capacitance, thereby enhancing the performance of interconnection structures by minimizing RC delays and improving signal routing in advanced semiconductor devices.
Implementation Method 1
achieved through specific deposition processes and the use of blocking layers to selectively deposit barrier and liner materials
Data Source
AI summary
An interconnection structure includes a conductive feature disposed in a first dielectric material, a first etch stop layer disposed over the first dielectric material, a second dielectric material disposed on the first etch stop layer, a conductive via extending through the second dielectric material and the first etch stop layer and in contact with at least a portion of the conductive feature, a first barrier layer disposed between the second dielectric material and the conductive via, a first liner disposed between and in contact with the first barrier layer and the conductive via, a third dielectric material disposed over the second dielectric material, a conductive line disposed in the third dielectric material and in direct contact with the conductive via, a second barrier layer disposed on the second dielectric material and in contact with the first barrier layer and the conductive line, and a second liner disposed between and in contact with the second barrier layer and the conductive line, wherein the second liner is separated from the first liner.