BEOL CMOS Inverter with Back-Gate Control for Short-Channel Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size of electronic components while minimizing short-channel effects and ensuring compatibility with existing devices during fabrication processes.
Innovation Solution
The development of a back-end-of-line (BEOL) CMOS inverter circuit with a twin conduction channel configuration and a back-gate electrode, utilizing metal-oxide semiconductor layers, which can be integrated with other BEOL components like capacitors and resistors, and fabricated at low temperatures to avoid damaging previous layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but short-channel effects increase and device performance deteriorates
Solution Approach 1:
The patent introduces a back-gate electrode positioned beneath the substrate, adding a vertical control dimension to the transistor structure. This allows channel control from both the top (front gate) and bottom (back gate), enabling effective management of short-channel effects even when the channel length is reduced for higher integration density.
Solution Approach 2:
The patent employs metal-oxide semiconductor materials with specific bandgap properties that provide inherent immunity to short-channel effects. The composite structure includes the semiconductor layer, gate dielectric, and back-gate electrode, creating a multi-material system that maintains device performance at scaled dimensions.
2Reliability
If fabrication temperature is increased to improve material properties, then device performance may improve, but previously fabricated devices are damaged
Solution Approach 1:
The patent utilizes metal-oxide semiconductor materials that can achieve desired electrical properties through low-temperature processing parameters. By adjusting deposition conditions, oxygen plasma treatment, and annealing temperatures within lower ranges, the BEOL devices attain optimal performance without subjecting FEOL devices to damaging high temperatures.
3Area of stationary object
If component size is reduced to increase integration, then more devices fit in a given area, but manufacturing precision requirements increase
Solution Approach 1:
By adding the back-gate electrode dimension, the patent provides an additional degree of freedom for device optimization. This vertical control mechanism allows for relaxed lateral dimension requirements, enabling smaller device footprints without proportionally increasing manufacturing precision demands in the planar directions.
Data Source
AI summary
An embodiment inverter circuit may include a gate electrode formed over an interlayer dielectric layer, a gate dielectric layer formed over the gate electrode, a first-conductivity-type semiconductor layer formed over the gate dielectric layer, a second-conductivity-type semiconductor layer formed over the gate dielectric layer and laterally displaced from the first-conductivity-type semiconductor layer, a first source electrode formed in contact with the first-conductivity-type semiconductor layer, a second source electrode formed in contact with the second-conductivity-type semiconductor layer, and a shared drain electrode formed in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. At least one of the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer may include a metal-oxide semiconductor and/or a multi-layer structure formed in a back-end-of-line (BEOL) process that may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.