BEOL Integration of Ion-Sensitive Transistors to Simplify Manufacturing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor manufacturing processes are complex and costly, particularly when integrating ion-sensitive transistors for life-science applications, as they require additional steps beyond the standard back-end-of-line (BEOL) processes.

Innovation Solution

Integrating ion-sensitive transistors with thin film transistors (TFTs) using indium gallium zinc oxide (IGZO) and high-k dielectric materials during the BEOL processes, simplifying the manufacturing process and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion-sensitive transistors are integrated using traditional separate processes, then functionality for life-science applications is achieved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvefunctionality for life-science applicationsVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the fabrication of ion-sensitive transistors with standard semiconductor BEOL processes. The sensing layer is formed as part of the interconnect structure during conventional manufacturing steps, eliminating the need for separate integration processes and reducing overall device complexity while maintaining life-science application functionality

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interconnect structure serves dual functions: it provides electrical connectivity and houses the sensing layer for ion detection. This multi-functional design allows the same manufacturing process to produce both standard semiconductor interconnects and ion-sensitive transistor components, reducing process complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If additional integration steps are added for ion-sensitive transistors, then sensing capability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvesensing capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The sensing layer material and deposition process are merged with existing BEOL interconnect materials and processes. By using the same deposition equipment and process steps for both interconnect formation and sensing layer creation, the patent avoids additional manufacturing costs while maintaining sensing capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The manufacturing process self-provides the sensing layer as part of the standard BEOL flow, eliminating the need for separate sensing layer deposition steps. The process uses existing materials and equipment to create both interconnect and sensing functions simultaneously

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Simplifies the semiconductor manufacturing process by integrating ion-sensitive transistors during BEOL, thereby lowering production costs while maintaining functionality for life-science applications.

Implementation Method 1

The target reacts with and/or binds to a sensing layer in the fluid to change a surface potential difference at the sensing layer

Methodology Applied
Scientific EffectSurface potential difference change:

Data Source

PatentUS12455259B2Semiconductor device and manufacturing method thereof
Publication Date: 2025.10.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12455259B2 patent drawing
  • US12455259B2 patent drawing
  • US12455259B2 patent drawing

AI summary

A semiconductor device includes a substrate, an interconnect, a second transistor, and a sensing film. The substrate includes devices disposed therein. The interconnect is disposed on the substrate and electrically coupled to the devices, where the interconnect includes a plurality of build-up layers and a through hole formed therein. The first transistor is disposed in the interconnect and vertically extends through at least one of the plurality of build-up layers, and the first transistor is electrically coupled to a first device of the devices through the interconnect. The second transistor is disposed in the interconnect and vertically extends through the at least one of the plurality of build-up layers, and the second transistor is electrically coupled to a second device of the devices through the interconnect, where the first transistor and the second transistor are laterally separated from one another through the through hole. The sensing film is disposed on the interconnect and further extends into the through hole, where the sensing layer is laterally disposed between the first transistor and the second transistor.