BEOL Memory Cell Arrays for In-Situ Data Processing
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Solution Overview
Problem
Existing BEOL memory devices are not entirely satisfactory in terms of data processing efficiency and integration density, as they require data transfer to a CPU for processing and lack flexibility in operation modes.
Innovation Solution
BEOL memory devices with memory cells arranged in arrays, featuring metal and semiconductor layers, via-like structures, and capacitors, allowing direct data processing without CPU intervention, and operating as both normal memory and in-situ data processing units simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred to CPU for processing, then processing capability is improved, but data transfer time and power consumption increase
Solution Approach 1:
The patent merges memory storage and data processing functions into a single integrated structure. Processing circuits are formed within the memory device itself, allowing data to be processed in-situ without transfer to external CPU, thereby eliminating data transfer time while maintaining processing capability
Solution Approach 2:
The patent introduces a new architectural dimension by implementing processing circuits at the memory device level rather than at the system level. This dimensional shift from system-level processing to device-level processing fundamentally changes the data flow architecture, enabling parallel processing operations within the memory array
2Productivity
If data is transferred to CPU for processing, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent combines memory and processing functions in a single integrated device, eliminating the need for data transfer between memory and CPU. This reduces power consumption by removing the energy required for data movement and by enabling processing to occur at the memory location where data resides
Solution Approach 2:
The memory device performs processing operations on its own stored data without requiring external CPU intervention. The processing circuits are self-contained within the memory device, allowing it to service its own data processing needs autonomously and efficiently
3Adaptability or versatility
If memory devices operate in traditional mode, then compatibility is maintained, but operational flexibility is reduced
Solution Approach 1:
The patent implements a memory device that can operate in multiple modes: traditional memory mode and in-situ processing mode. The same hardware structure supports both conventional read/write operations and neural network inference operations, providing operational flexibility without requiring separate dedicated processing units
Solution Approach 2:
The patent enables dynamic mode switching where the memory device can transition between traditional memory operations and processing operations based on computational needs. This dynamic adaptability allows the system to optimize performance by selecting the appropriate operational mode for different workloads
4Productivity
If integration density is increased by reducing feature size, then component count is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges memory structures and processing circuits into a unified fabrication process. Both components are formed using the same semiconductor manufacturing steps, which simplifies production and reduces the need for additional lithography layers and alignment processes that would otherwise be required for separate memory and processor fabrication
Data Source
AI summary
A memory device includes a plurality of memory cells. Each of the plurality of memory cells includes a capacitor configured to store an amount of electrical charges, and a plurality of transistors electrically coupled to the capacitor. Based on a pulse signal, a first subset of the plurality of transistors are configured to form a first conduction path, and a second subset of the plurality of transistors are configured to form a second conduction path. The amount of electrical charges is configured to be altered through the first conduction path and the second conduction path.