BEOL Memory-Over-Logic Layout for Faster In-Memory Computing
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating memory arrays with logic structures, leading to increased manufacturing costs, complexity, and reduced processing speed due to separate memory and logic components.
Innovation Solution
The memory array is positioned to overlie the logic structure or interconnection layers, enabling in-memory computing and near-memory computing, which reduces manufacturing costs and complexity while increasing memory cell density and processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory arrays and logic structures are integrated, then processing speed and memory cell density are improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines memory arrays and logic structures into a single integrated device, placing the memory array over the logic structure or interconnection layers. This merging eliminates the need for separate memory and logic components, thereby improving processing speed through reduced data transfer distances and increasing memory cell density through shared substrate space.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration, positioning the memory array vertically over the logic structure. This vertical integration approach increases memory cell density by utilizing the third dimension while maintaining manufacturing feasibility through established semiconductor stacking techniques.
2Ease of manufacture
If memory arrays and logic structures are integrated, then manufacturing costs are reduced, but device complexity increases
Solution Approach 1:
The patent merges memory arrays and logic structures into a single device, eliminating the need for separate manufacturing processes for discrete memory and logic components. This integration reduces manufacturing costs by consolidating fabrication steps, reducing assembly operations, and enabling economies of scale, while the increased device complexity is managed through systematic design approaches.
3Device complexity
If separate memory and logic components are used, then device complexity is reduced, but processing speed decreases
Solution Approach 1:
The patent employs vertical stacking to position the memory array over the logic structure, creating a three-dimensional architecture. This spatial reorganization reduces the horizontal distance between memory and logic components, enabling faster data transfer and processing speeds while maintaining manageable device complexity through modular design.
4Quantity of substance
If memory arrays are positioned to overlie logic structures, then memory cell density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes vertical stacking to achieve high memory cell density by positioning the memory array over the logic structure in the third dimension. This approach increases density without requiring proportional increases in lateral precision, as the vertical alignment can be achieved through established semiconductor techniques such as self-alignment and precision etching.
Solution Approach 2:
The patent employs preliminary alignment features and self-alignment techniques during the fabrication process to ensure precise positioning of the memory array over the logic structure. By pre-defining alignment markers and using sequential deposition and etching steps, the manufacturing precision requirements are managed systematically before final assembly.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a logic structure overlying a semiconductor substrate of the semiconductor device. The logic structure includes a plurality of logic cells. The semiconductor device includes one or more interconnection layers, overlying the logic structure, in a Back End of Line (BEOL) structure of the semiconductor device. The semiconductor device includes a non-volatile memory array, including a plurality of memory cells, overlying the logic structure and the one or more interconnection layers, wherein the non-volatile memory array at least one of overlies or is within the BEOL structure.