BEOL Memory Selector Layout for High-Density Write Current
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density non-volatile memory devices due to the front-end-of-line (FEOL) transistor bottleneck, which requires high write current, leading to increased transistor dimensions or multiple transistors per memory element, resulting in area penalties and reduced integration density.
Innovation Solution
The implementation of a back-end-of-line (BEOL) transistor as a selector within the memory device's interconnect structure, featuring a vertical gate-all-around structure with a selector channel and gate electrode, allowing for better gate control and eliminating wiring connections between the memory cell and selector, thereby freeing up front-end space for more integration flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FEOL transistors are used as selectors, then write current can be achieved, but transistor dimensions must be enlarged or multiple transistors per memory element are required, resulting in area penalties
Solution Approach 1:
The patent transitions the selector from FEOL to BEOL, moving it to a different dimensional layer in the fabrication process. This allows the selector to be formed after the memory cell stack, enabling direct connection to the bottom electrode without requiring large FEOL transistor structures. The BEOL selector uses a planar or shallow trench structure that occupies minimal area compared to FEOL transistors.
Solution Approach 2:
The selector function is extracted from the FEOL transistor and placed in the BEOL interconnect layer. This separation allows the memory cell stack to be formed independently in FEOL, while the selector is formed separately in BEOL, eliminating the area penalty associated with large FEOL transistors per memory element.
2Power
If FEOL transistors are used as selectors, then write current can be achieved, but integration density is reduced
Solution Approach 1:
By moving the selector to BEOL, the patent enables a stacked memory architecture where multiple memory cell stacks can be integrated vertically. The BEOL selector occupies horizontal space in the interconnect layer rather than requiring vertical space in the FEOL transistor region, thereby increasing integration density.
Solution Approach 2:
The BEOL selector is merged with the interconnect structure, sharing the same fabrication process and material layers. This integration eliminates separate wiring connections and reduces the overall device footprint, improving integration density while maintaining write current capability.
3Reliability
If wiring connections are made between memory cell and selector, then electrical connection is achieved, but front-end space is consumed
Solution Approach 1:
The BEOL selector is merged with the interconnect structure, sharing the same fabrication process and material layers. This integration eliminates separate wiring connections and reduces the overall device footprint, improving integration density while maintaining write current capability.
Solution Approach 2:
The BEOL selector structure serves dual functions: it provides the selector function and simultaneously acts as the interconnect wiring. The bottom electrode of the memory cell directly contacts the BEOL selector, eliminating the need for separate wiring connections and freeing up front-end space.
Data Source
AI summary
The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.