BEOL Memory Array Layout With Under-Array Peripheral Circuitry
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Solution Overview
Problem
The challenge in integrated circuit (IC) design is to efficiently access multiple back-end memory arrays in a reduced footprint, as existing architectures face difficulties in routing numerous bit lines and word lines from multiple memory cell levels to peripheral circuitry, leading to increased space requirements and reduced space efficiency.
Innovation Solution
The implementation of a differential sense amplifier and level selection circuitry positioned partially or entirely within the footprint area under the memory arrays, along with word line driver circuits, allows for efficient bit line and word line routing, enabling access to multiple memory arrays with reduced horizontal distance between array levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If peripheral circuitry is positioned at the periphery of memory arrays, then routing of bit lines and word lines becomes simpler, but the horizontal distance between array levels increases and footprint area expands
Solution Approach 1:
The patent positions peripheral circuitry in the vertical dimension by placing it in BEOL layers underneath the memory arrays rather than at the horizontal periphery. This allows bit lines and word lines to be routed vertically through interconnect layers, reducing the horizontal footprint while maintaining routing simplicity through structured vertical interconnection schemes.
Solution Approach 2:
The patent nests peripheral circuitry within the footprint area of the memory arrays by placing it in underlying BEOL layers. This nested configuration allows the peripheral circuitry to be contained within the vertical projection of the memory array footprint, effectively utilizing the three-dimensional space without increasing the horizontal area.
2Area of stationary object
If peripheral circuitry is positioned under memory arrays in BEOL, then footprint area is reduced, but routing of numerous lines from multiple levels becomes more difficult
Solution Approach 1:
The patent segments the interconnect structure into multiple BEOL layers, each handling specific routing functions. This segmentation allows different sets of bit lines and word lines to be routed through different vertical pathways and interconnect layers, reducing the complexity of routing numerous lines from multiple memory levels by distributing the routing burden across multiple structured segments.
Solution Approach 2:
The patent introduces intermediate interconnect layers and redistribution structures as mediators between the peripheral circuitry in BEOL and the memory arrays. These intermediary structures facilitate the complex routing by providing structured connection points and redistribution pathways, making it easier to connect numerous lines from multiple levels to the underlying peripheral circuitry.
3Quantity of substance
If more than one level of memory cells is implemented in BEOL, then memory capacity increases, but routing of data lines to periphery circuitry requires significant area
Solution Approach 1:
The patent utilizes the vertical dimension by implementing multiple memory cell levels in BEOL layers stacked vertically. This three-dimensional arrangement allows increased memory capacity within the same horizontal footprint, as data lines can be routed vertically through interconnect layers to access different memory levels without requiring additional horizontal routing area.
Solution Approach 2:
The patent merges multiple memory levels and their associated data line routing into a unified vertical interconnect structure. By combining the routing of data lines from multiple levels through shared vertical pathways and redistribution layers, the patent reduces the total routing area required compared to separate horizontal routing for each memory level.
Data Source
AI summary
Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.