BEOL Fine Metal Line Layout Using Spacer Patterning to Prevent Clogging
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving uniformity and preventing clogging during the formation of fine metal lines in back-end-of-line (BEOL) structures, which affects the quality and alignment of semiconductor devices due to difficulties in patterning and etching processes.
Innovation Solution
The approach involves forming both fine and wide metal lines using different materials, with fine metal lines having a uniform width and pitch, and wide metal lines wider than twice the fine metal lines, achieved through a method that includes forming a metal layer, patterning with photoresist, conformal deposition of a spacer layer, and selective etching to avoid clogging and ensure uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If subtractive etching is used to pattern fine metal lines, then metal lines can be formed, but clogging occurs between hardmask or spacer patterns preventing uniform fine metal line formation
Solution Approach 1:
The patent segments the metal line formation process into two distinct approaches: fine metal lines are formed using spacer-based self-aligned patterning, while wide metal lines are formed using direct photolithography patterning. This segmentation prevents clogging issues from affecting fine line formation by using a different patterning mechanism that doesn't rely on removing material between closely spaced patterns.
Solution Approach 2:
Instead of using subtractive etching to remove metal between patterns (the conventional approach), the patent uses additive deposition to form metal lines conformally on spacer structures. This inversion of the patterning approach eliminates clogging problems by building up material rather than removing it, ensuring uniform fine metal line formation.
2Manufacturing precision
If hardmask or spacer layer is patterned down into metal layer by etching, then metal lines can be formed, but spaces between fine metal lines have different widths due to clogging
Solution Approach 1:
The patent employs self-aligned double patterning (SADP) where spacers automatically form aligned to the metal patterns without requiring additional alignment steps. The spacers serve both as patterning masks and as defining structures for the final metal line positions, eliminating the need for complex multi-step alignment processes while ensuring uniform spacing.
Solution Approach 2:
The patent changes the critical dimension control parameter from etch depth and mask thickness to spacer film thickness. By controlling the spacer deposition thickness uniformly through conformal deposition, the spacing between fine metal lines is precisely controlled, achieving width uniformity without complex etching parameter optimization.
3Productivity
If fine metal lines with high aspect ratio and narrow spacing are formed, then device density increases, but clogging occurs and uniformity cannot be achieved
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional conformal deposition by forming spacers on the vertical sidewalls of metal patterns. This dimensional change allows fine metal lines with high aspect ratios to be formed with uniform spacing, as the spacer thickness (controlled by deposition) directly determines the horizontal spacing between lines regardless of the vertical height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of uniform fine metal lines and wide metal lines, improving the alignment and quality of semiconductor devices by preventing clogging and ensuring consistent spacing and width, thus addressing the limitations of traditional etching methods.
Implementation Method 1
a spacer layer is conformally deposited on outer surfaces of the plurality of metal patterns
Data Source
AI summary
Provided is a semiconductor device including a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line.