3D BEOL MIM Capacitor Using Deep Vias to Save Chip Area
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Solution Overview
Problem
On-chip MIM capacitors have limited capacitance values due to their small size, and deep trench MIM technology in the FEOL requires additional substrate area and suffers from signal interference, necessitating a method to enhance capacitance while minimizing chip area usage.
Innovation Solution
A 3D MIM structure is formed in the BEOL using deep via holes through multiple dielectric layers, allowing for a large capacitance value without increasing the chip area, and the formation of electrodes within the via structure without additional fabrication steps, using a conductive etch stop structure to protect underlying metallization layers during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a standard planar capacitor is used, then the chip area is small, but the capacitance value is limited
Solution Approach 1:
The patent transitions from a planar 2D capacitor structure to a 3D vertical capacitor structure by forming deep via holes through multiple dielectric layers. This dimensional change allows the capacitor electrodes to extend vertically through the substrate, dramatically increasing the effective capacitance area without occupying additional chip surface area, thus resolving the contradiction between capacitance value and chip area.
Solution Approach 2:
The capacitor structure is nested within the existing via hole structure and dielectric layers of the semiconductor device. The first and second electrodes are formed within the deep via hole, utilizing the vertical space already present in the device architecture. This nesting approach enables high capacitance density by effectively using the third dimension (depth) without adding lateral footprint.
2Quantity of substance
If a deep trench MIM capacitor is formed in the FEOL, then the capacitance value is large, but additional substrate area is required and signal interference occurs
Solution Approach 1:
The patent introduces a conductive etch stop structure as an intermediary element formed at a specific depth within the via hole. This conductive layer serves multiple functions: it protects underlying metallization layers during the etching process, provides an additional electrode surface for capacitance formation, and acts as a shield to reduce signal interference with adjacent circuits. The etch stop structure enables the formation of high capacitance values while maintaining electrical isolation and reducing harmful electromagnetic interference.
3Quantity of substance
If electrodes are formed within via structures, then capacitance is enhanced, but additional fabrication steps are required
Solution Approach 1:
The patent merges the capacitor electrode formation process with the existing via hole fabrication process. The same etching steps used to create via holes for interconnects are also used to form the deep via holes for capacitors. The conductive etch stop structure is formed using the same deposition processes as other metallization layers. By combining these functions into a unified fabrication sequence, the patent achieves enhanced capacitance values without significantly increasing fabrication process complexity.
Solution Approach 2:
The deep via hole structure serves multiple functions: it acts as both an interconnect pathway and a capacitor formation region. The conductive etch stop structure simultaneously provides etch protection, forms an additional electrode, and reduces signal interference. This multi-functionality approach allows the fabrication process to achieve multiple objectives (via formation, capacitor creation, signal shielding) in a single integrated process flow, avoiding the need for separate dedicated capacitor fabrication steps.
Data Source
AI summary
Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process. In one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.