BEOL MIM OTP Memory Structure for High Breakdown Voltage
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Solution Overview
Problem
The semiconductor industry faces challenges in forming one-time-programmable (OTP) memory devices with high-voltage endurance and reliability as devices shrink in dimensions, leading to topography issues and breakdown of gate oxide layers, which are not adequately addressed by existing technologies.
Innovation Solution
The formation of OTP memory devices and high-resistance resistors in back-end of line (BEOL) processes using a metal-insulator-metal (MIM) construction with a U-shaped breakdown layer surrounding a top electrode, reducing circuit area and production costs associated with photolithography masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage devices are formed with larger dimensions, then reliability and breakdown voltage are improved, but device area increases causing topography issues and compressing room for other features
Solution Approach 1:
The patent transitions OTP memory device formation from front-end-of-line (FEOL) to back-end-of-line (BEOL) processing stages. This dimensional shift in the manufacturing timeline allows high voltage devices to be formed after low voltage devices are already in place, enabling better spatial arrangement and reduced device area while maintaining reliability through separate processing optimization
Solution Approach 2:
The patent changes the operating voltage parameter by forming high voltage devices (20V breakdown voltage) in BEOL processes rather than FEOL. This parameter change allows the use of thicker dielectric layers and different material stacks in later processing stages, achieving high breakdown voltage with reduced device footprint
2Reliability
If high voltage devices are formed with larger dimensions, then breakdown voltage is improved, but device complexity and processing complexity increase
Solution Approach 1:
The patent segments the manufacturing process into distinct FEOL and BEOL stages, with low voltage devices formed in FEOL and high voltage devices formed in BEOL. This segmentation allows each process stage to be optimized independently, reducing overall processing complexity while maintaining high breakdown voltage through specialized BEOL high voltage device structures
Solution Approach 2:
By moving high voltage device formation to the BEOL dimension (later processing stage), the patent simplifies the FEOL process and allows high voltage devices to share BEOL interconnect layers and dielectric structures with low voltage devices, reducing overall device complexity and processing steps
3Ease of manufacture
If conventional OTP memory structures are used, then programming functionality is achieved, but gate oxide layers break down due to high operating voltage
Solution Approach 1:
The patent creates a copy of the OTP memory device functionality in the BEOL using a metal-insulator-metal (MIM) structure with a breakdown layer, rather than using the conventional FEOL transistor gate oxide approach. This copying of the programming function to a different structural platform eliminates the gate oxide breakdown issue while maintaining one-time programmable functionality
Solution Approach 2:
The patent introduces a MIM structure with a breakdown layer as an intermediary between the control electrode and the storage node, replacing the direct gate oxide approach. This intermediary structure allows high voltage operation for programming without subjecting a thin gate oxide to breakdown conditions, as the breakdown occurs in a dedicated breakdown layer designed for this purpose
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device dimensions and production costs while enhancing the reliability and breakdown voltage of OTP memory devices, allowing for simultaneous formation of OTP memory devices and high-resistance resistors in BEOL structures, improving manufacturing efficiency and device performance.
Implementation Method 1
depositing a high-k dielectric layer over the opening
Implementation Method 2
depositing a metal layer over the high-k dielectric layer
Data Source
AI summary
a transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.