BEOL MSM Diode ESD Circuit for Low-Area 3D Packaging

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Solution Overview

Problem

Existing ESD protection circuits in semiconductor packaging require costly front-end processes, consume significant silicon area, and hinder 3D architecture design capabilities due to doping, diffusion, thermal annealing, and shallow trench isolation, increasing fabrication costs and complexity.

Innovation Solution

Integration of metal-semiconductor-metal (MSM) diodes between metal layers of a substrate using the back-end-of-line (BEOL) process, eliminating the need for front-end processes and reducing silicon consumption, while enabling improved circuit design and area efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If front-end processes (doping, diffusion, thermal annealing, shallow trench isolation) are used for ESD protection circuits, then ESD protection functionality is achieved, but fabrication cost and process complexity increase

Engineering Contradiction:
ImproveESD protection functionalityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the ESD protection circuit fabrication from the front-end process and relocates it to the back-end process. Specifically, the ESD protection circuits are formed after the active devices are completed, using the existing metal interconnect layers and vias rather than requiring separate front-end doping and isolation steps. This extraction eliminates the need for costly front-end processes while maintaining ESD protection functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent utilizes existing metal interconnect layers and vias that are already part of the standard CMOS fabrication process for their intended purpose of electrical interconnection. These metal structures are then repurposed to form ESD protection circuits, effectively using 'disposable' or already-present materials rather than requiring additional expensive front-end process steps.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If front-end processes are used for ESD protection circuits, then ESD protection is provided, but silicon area consumption increases

Engineering Contradiction:
ImproveESD protection functionalityVSAvoidsilicon area consumption
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the ESD protection circuit functionality with the existing metal interconnect structure. The ESD protection circuits share the same metal layers and vias that are already present for signal and power distribution. This merging allows ESD protection to be provided without consuming additional silicon area, as the metal structures serve dual purposes: both interconnection and ESD protection.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The metal interconnect layers and vias are designed to serve multiple functions: electrical interconnection between devices and ESD protection. By making the metal structures universal, the patent eliminates the need for dedicated ESD protection structures that would consume additional silicon area, thereby achieving area efficiency while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If front-end processes are used for ESD protection circuits, then ESD protection is achieved, but 3D architecture design capabilities are hindered

Engineering Contradiction:
ImproveESD protection functionalityVSAvoid3D architecture design capabilities
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

Instead of the conventional approach of forming ESD protection circuits during front-end processing, the patent inverts the sequence by forming ESD protection circuits during back-end processing. This inversion allows the active devices and their interconnects to be fully designed and fabricated first, enabling flexible 3D architecture design, and then the ESD protection is added in subsequent metal layers without constraining the earlier design decisions.

Inventive Principle:
Principle #13The other way round (Inversion)

4Reliability

If front-end processes are used for ESD protection circuits, then ESD protection functionality is achieved, but fabrication cost increases

Engineering Contradiction:
ImproveESD protection functionalityVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts the ESD protection circuit fabrication from the expensive front-end process and relocates it to the lower-cost back-end process. By forming ESD protection circuits after the active devices are completed and using existing metal interconnect layers, the patent eliminates the need for costly front-end doping, diffusion, and thermal annealing steps, thereby reducing overall fabrication cost while maintaining ESD protection functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces fabrication costs, minimizes silicon area usage, and enhances circuit design capabilities without increasing complexity, facilitating 3D architecture designs.

Implementation Method 1

electrostatic discharge (ESD) circuit with diodes in metal layers of a substrate

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentEP4203033B1Electrostatic discharge (ESD) circuit with diodes in metal layers of a substrate
Publication Date: 2026.02.25 INTEL CORP
  • EP4203033B1 patent drawingFigure 1
  • EP4203033B1 patent drawingFigure 1
  • EP4203033B1 patent drawingFigure 2

AI summary

Embodiments described herein may be related to apparatuses, processes, and techniques related to an ESD protection circuit that includes diodes in the BEOL metal layers of a substrate. In embodiments, the diodes may be MSM diodes. Other embodiments may be described and/or claimed.