BEOL Non-Planar Transistors Using Amorphous Oxide Semiconductors

The patent divides the transistor fabrication process into two distinct segments: FEOL processes for initial transistor formation and BEOL processes for additional transistor formation. This segmentation allows different thermal budgets to be applied to different portions of the die, enabling high-temperature FEOL processing without damaging BEOL components, and subsequently enabling BEOL transistor formation at lower temperatures that preserve existing BEOL structures.

The patent transitions from two-dimensional planar transistor integration to three-dimensional integration by forming transistors in both the FEOL and BEOL portions of the die. This vertical stacking approach allows transistors to be integrated in multiple layers, dramatically increasing transistor density without requiring proportional increases in die area, while the BEOL transistors are formed at temperatures compatible with existing BEOL structures.

The patent segments the die into FEOL and BEOL portions with distinct transistor integration schemes. The FEOL portion contains traditional planar transistors formed at high temperatures, while the BEOL portion contains transistors formed at lower temperatures. This segmentation enables each region to be optimized for its specific requirements, achieving high overall transistor density while maintaining manufacturing feasibility through established process separation.

The patent employs composite material structures in the BEOL transistors, utilizing amorphous oxide semiconductor channels combined with metal gates and various dielectric layers. This composite approach enables transistor formation at BEOL-compatible temperatures while achieving superior electrostatic control and performance, thereby increasing functionality per unit area without proportionally increasing device complexity.

The patent utilizes the vertical dimension by integrating transistors in both the FEOL and BEOL portions of the die, effectively stacking transistor layers. This three-dimensional integration approach dramatically improves die area utilization, as transistors are distributed throughout the vertical depth of the die rather than being confined to a single planar layer, thereby increasing the number of transistors per unit area without requiring larger die dimensions.

The patent makes the BEOL portion multi-functional by enabling it to serve both as the interconnect region and as a transistor integration region. The BEOL structures (interconnect lines, vias, and dielectric layers) simultaneously provide electrical connectivity and serve as the foundation for transistor formation, thereby improving die area utilization without adding separate dedicated transistor regions or complicating the manufacturing process.