Semiconductor Pad Protection Layout for BEOL Packaging Stress

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Solution Overview

Problem

Chip packaging interaction (CPI) induces mechanical stress, leading to cracking in semiconductor structures such as the extreme low K (ELK) layer and metal-insulator-metal (MIM) devices during the Back End of Line (BEOL) process, due to bonding pressure from conductive bumps, resulting in device failure.

Innovation Solution

A protecting structure is disposed on the dielectric surface of the metallization structure, leveled with the conductive pad, comprising silicon nitride or silicon oxide, and enhanced with spacers and a polymer layer to absorb and disperse mechanical stress, thereby reducing the impact of CPI on underlying structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive bumps are bonded to the conductive pad during BEOL process, then electrical connection is established, but mechanical stress from chip packaging interaction causes cracking in ELK layer and MIM devices

Engineering Contradiction:

Improvedevice reliabilityVSAvoidmechanical stress from CPI

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A protecting structure comprising silicon nitride or silicon oxide is introduced as an intermediary layer between the conductive pad and the underlying ELK layer/MIM devices. This protecting structure absorbs and disperses the mechanical stress generated during chip packaging interaction, preventing stress transmission to the sensitive underlying structures while maintaining electrical connectivity through the conductive bump-pad interface

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The protecting structure is formed in advance on the dielectric surface before the conductive bump bonding process. This pre-formed structure acts as a cushioning layer that anticipates and mitigates the mechanical stress that will be generated during subsequent chip packaging operations, preventing cracking in the ELK layer and MIM devices before they can occur

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Strength

If protecting structure is added to reduce mechanical stress, then structural integrity of ELK layer and MIM devices is improved, but device complexity increases

Engineering Contradiction:

Improvestructural integrityVSAvoidstructure complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The protecting structure is selectively formed only in specific regions where mechanical stress concentration occurs during chip packaging, rather than uniformly across the entire device. This localized approach provides stress protection to critical areas (ELK layer and MIM devices) while minimizing the overall addition to device complexity and maintaining manufacturing efficiency

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11830832B2Semiconductor structure and manufacturing method thereof

Publication Date: 2023.11.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.