BEOL Passive Circuit Layout for Lower RF Signal Loss

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Solution Overview

Problem

Existing on-chip passive circuits in silicon technologies suffer from high loss due to thin metal thicknesses and low substrate resistivity, limiting high-frequency circuit and system performance in mobile electronic devices.

Innovation Solution

Fabricating passive circuits on the C4 connection layer of the BEOL, which is significantly taller than the substrate layers, allowing for lower loss and higher current capacity by moving these circuits further away from the silicon substrate, and using a standard bump process with minimal modifications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If passive circuits are fabricated on thin substrate layers, then manufacturing is easier, but signal loss increases and current capacity decreases

Engineering Contradiction:
Improveease of manufactureVSAvoidsignal loss
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent transitions passive circuits from planar substrate layers to a three-dimensional BEOL structure with significant vertical height (18 μm). This dimensional change allows circuits to be positioned away from the lossy silicon substrate while maintaining ease of manufacture through standard bump processes, thereby reducing signal loss without sacrificing manufacturability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The BEOL structure acts as an intermediary between the silicon substrate and the passive circuits. By placing circuits on the BEOL rather than directly on the substrate, the patent eliminates direct interaction with the lossy substrate while maintaining electrical connectivity, thus reducing signal loss without complicating the manufacturing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If passive circuits are placed closer to the silicon substrate, then device complexity is reduced, but signal loss increases

Engineering Contradiction:
Improvedevice complexityVSAvoidsignal loss
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent utilizes the vertical dimension of the BEOL structure to position passive circuits away from the silicon substrate. This spatial separation in the vertical dimension reduces signal loss by distancing circuits from the lossy substrate, while the BEOL integration maintains relatively simple device architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of energy

If metal thickness is increased to reduce signal loss, then current capacity improves, but manufacturing complexity increases

Engineering Contradiction:
Improvesignal lossVSAvoidmanufacturing complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The BEOL structure serves as an intermediary platform that provides sufficient vertical height (18 μm) to accommodate passive circuits with adequate current capacity. This approach achieves the desired current capacity without requiring increased metal thickness, thereby avoiding additional manufacturing complexity while still reducing signal loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12598996B2Passive circuit on a back-end-of-line of a package
Publication Date: 2026.04.07 INTEL CORP
  • US12598996B2 patent drawing
  • US12598996B2 patent drawing
  • US12598996B2 patent drawing

AI summary

Embodiments herein relate to systems, apparatuses, or processes directed to fabricating passive circuits on a surface of a BEOL of a package, for example on a C4 connection layer of the BEOL. In embodiments, the passive circuits may be fabricated using a standard bump process. Other embodiments may be described and/or claimed.