Customizable Logic Cell Using BEOL Reconfiguration for Logic Inversion
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Solution Overview
Problem
The manufacturing of integrated circuits (ICs) faces errors and defects in back end of line (BEOL) layers, leading to logic inversion issues where gates act incorrectly, requiring re-manufacturing or additional components that cause timing delays and occupy additional surface area.
Innovation Solution
A customizable logic cell structure comprising pairs of complementary transistors connected in series between voltage nodes, with BEOL layers controlling their functionality to correct logic inversion errors without full re-manufacturing, allowing the structure to function as either a buffer or inverter by setting voltage nodes to opposite logic levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional inverters or buffers are integrated into the device structure to correct logic inversion, then logic inversion errors are corrected, but timing delays increase and surface area occupancy increases
Solution Approach 1:
The patent inverts the conventional approach by making the BEOL layers programmable and reconfigurable. Instead of adding fixed inverters/buffers to correct logic errors, the invention allows the BEOL interconnections themselves to be dynamically configured to implement correction logic, thereby avoiding additional timing delays and surface area requirements.
Solution Approach 2:
The invention introduces dynamic reconfigurability to the BEOL layers through programmable interconnections. This allows the logic cell to adapt its behavior (including logic inversion correction) after manufacturing, eliminating the need for static additional components that would cause timing delays and occupy surface area.
2Reliability
If additional inverters or buffers are integrated into the device structure to correct logic inversion, then logic inversion errors are corrected, but surface area occupancy increases
Solution Approach 1:
The patent makes the BEOL layers universal and multi-functional by enabling them to perform both their original interconnection function and logic inversion correction function. This eliminates the need for dedicated additional inverters or buffers, thereby preventing surface area increase while maintaining correction capability.
Solution Approach 2:
The invention inverts the conventional division of labor where device layer components perform logic functions and BEOL layers perform only interconnection. Instead, the BEOL layers are empowered to perform logic correction functions, eliminating the need for additional surface area-consuming components.
3Reliability
If BEOL layers are re-manufactured to correct logic inversion errors, then logic inversion is corrected, but manufacturing complexity and cost increase
Solution Approach 1:
The patent incorporates preliminary action by building reconfigurability and programmability into the BEOL layers during manufacturing. This preliminary capability allows logic inversion errors to be corrected through software/configuration updates rather than requiring costly and complex re-manufacturing of the entire device layer or BEOL layers.
Data Source
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AI summary
Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure (100) of the disclosure includes a first pair of complementary transistors (112) connected in series between a first voltage node (V1) and a second voltage node (V2). Each transistor of the first pair includes a gate coupled to a first input node (N1). A second pair of complementary transistors (114) is connected in series between the first voltage node (V1) and the second voltage node (V2) in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node (N2). An output line (Vout) is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.