Embedded BEOL Resistor Sidewall Removal
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Solution Overview
Problem
Existing methods for forming thin film resistors embedded in interconnect dielectric material in semiconductor devices are complex, expensive, and prone to topography issues, Joule heating, and poor scaling capabilities, which affect precision and integration in analog circuits.
Innovation Solution
A semiconductor structure with a resistor embedded in an interconnect dielectric material layer, where a diffusion barrier material is used at the bottom of a feature, and the sidewall portions of the diffusion barrier liner are removed to reduce parasitic noise and improve precision, ensuring the resistor's top surface is beneath the interconnect dielectric layer, and a dielectric cap covers the resistor to minimize contact with metallic structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin film resistor is embedded in an interconnect dielectric material using prior art methods, then the resistor can be formed in the BEOL, but the process becomes complicated and expensive
Solution Approach 1:
The patent merges the resistor formation process with the existing interconnect dielectric material deposition process. The diffusion barrier liner is formed as part of the interconnect structure, and the resistor is created by removing sidewall portions of this liner rather than through a separate embedding process. This integration eliminates complex multi-step procedures while maintaining reliable resistor formation in the BEOL.
2Reliability
If a thin film resistor is embedded in an interconnect dielectric material, then the resistor can be integrated into the chip, but topography issues arise that degrade chip yield
Solution Approach 1:
The patent applies local quality by creating a planarized region specifically at the resistor location through selective removal of sidewall portions of the diffusion barrier liner. The dielectric material is deposited to a uniform topography, and the resistor region is locally prepared by etching away sidewalls to create a flat surface, ensuring uniform electrical properties and eliminating topography-induced yield degradation while maintaining overall chip integration.
3Measurement precision
If sidewall portions of a diffusion barrier liner are removed to reduce parasitic noise, then resistor precision improves, but additional processing steps are required
Solution Approach 1:
The patent combines the sidewall removal step with the existing diffusion barrier liner formation process. The diffusion barrier liner is deposited with the interconnect structure, and the same etch process used for interconnect patterning is employed to remove the sidewall portions. This merging of operations achieves improved resistor precision through parasitic noise reduction without adding significant processing complexity, as the sidewall removal is performed concurrently with standard interconnect fabrication steps.
4Measurement precision
If the resistor topmost surface is located beneath the interconnect dielectric material layer, then parasitic noise is reduced, but access to the resistor becomes more difficult
Solution Approach 1:
The patent introduces an intermediary structure - a contact opening through the interconnect dielectric material layer - that provides access to the embedded resistor. The resistor is positioned beneath the dielectric layer to reduce parasitic noise, and the contact opening serves as an intermediary pathway that allows electrical connection without exposing the resistor surface. This intermediary approach maintains both the noise reduction benefit of embedding and the operational accessibility needed for circuit functionality.
Data Source
AI summary
A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.