BEOL Resistor Structure Using Trenches to Increase Circuit Density
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Solution Overview
Problem
The increasing complexity of implementing semiconductor circuit elements, such as active and passive devices, due to scaling down in dimensions, necessitates more efficient use of available area in semiconductor devices to enhance functionality and performance.
Innovation Solution
The integration of resistor structures in the back end of line (BEOL) region of semiconductor devices, comprising a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer, which allows for the fabrication of passive devices like resistors, thereby increasing the available area for additional active and passive devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit elements are scaled down in dimensions to increase storage capacity and processing speed, then higher storage capacity and faster processing are achieved, but implementation complexity increases
Solution Approach 1:
The patent utilizes the back-end-of-line (BEOL) region, which is traditionally unused or underutilized, to fabricate passive devices such as resistors. This represents a dimensional shift from using only the front-end device region to incorporating the entire vertical and lateral structure including interconnect layers. By deploying resistors in the BEOL region with multiple interconnect layers, the patent effectively adds a new spatial dimension for device placement, thereby increasing functional density without complicating the core active device fabrication process
Solution Approach 2:
The BEOL region, originally designed solely for interconnect functions, is transformed into a multi-functional area that simultaneously serves as both interconnect routing and housing for passive devices like resistors. This universal utilization of the BEOL region allows it to perform multiple functions: electrical interconnection between active devices and passive circuit elements, thereby reducing the need for separate dedicated areas and simplifying overall device architecture
2Adaptability or versatility
If the available area in semiconductor devices is increased for additional active and passive devices, then functionality and performance are enhanced, but device area consumption increases
Solution Approach 1:
The patent exploits the vertical dimension by utilizing upper interconnect layers (e.g., fifth, sixth, seventh metal layers) and the BEOL region that extend above the active device region. By placing resistors in these upper layers rather than in the planar substrate area, the patent effectively uses the vertical z-dimension for device placement, thereby accommodating additional functionality without increasing the chip footprint
Solution Approach 2:
The resistor structure is nested within the existing interconnect layer architecture. The resistor is formed by utilizing conductive materials from the interconnect layers themselves, nesting the passive device function within the already-present conductive structure. This nested approach allows the resistor to share space with the interconnect system rather than requiring separate dedicated area
Data Source
AI summary
The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.