BEOL Metal Routing Layout for Higher Current Density
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Solution Overview
Problem
Conventional back end of line (BEOL) structures in semiconductor devices suffer from inefficient current density distribution due to non-uniform routing widths and spacing of metal layers, leading to increased resistance and reduced thermal and electrical performance.
Innovation Solution
Implementing a BEOL structure with uniformly wide metal routings, a redesigned via layer, and a selective insulation layer to optimize current flow patterns, allowing for a more efficient use of space and improved current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-uniform routing widths and spacing are used in conventional BEOL structures, then manufacturing complexity is reduced, but current density distribution becomes inefficient and resistance increases
Solution Approach 1:
The patent applies local quality by making different portions of the metal routing layers have different widths. Specifically, the first metal routing layer has a first width in a first portion and a second width in a second portion, and similarly for the second metal routing layer. This allows optimization of current density distribution in different regions of the BEOL structure, improving electrical performance while maintaining manufacturing feasibility.
2Reliability
If uniform metal routing widths are implemented, then current density and thermal performance improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the metal routing layers into different portions with different widths. The first metal routing layer is divided into a first portion with a first width and a second portion with a second width, and the second metal routing layer is similarly segmented. This segmentation allows each portion to be optimized for its specific function while maintaining overall manufacturing feasibility through standardized fabrication processes.
3Reliability
If optimized via layer and insulation layer are added, then current flow patterns improve, but device complexity increases
Solution Approach 1:
The patent introduces an insulation layer as an intermediary between the first and second metal routing layers. This insulation layer, with its first and second portions, mediates the interaction between the metal layers and enables optimized current flow patterns. The via layer also acts as an intermediary, providing controlled connections between layers and improving overall current distribution efficiency.
Data Source
AI summary
A semiconductor device is described herein. The semiconductor device generally includes a metal fabrication layer disposed on a substrate. The semiconductor device generally includes a dielectric layer having a first plurality of vias aligned with a first metallization region of the metal fabrication layer and a second plurality of vias aligned with a second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer. The semiconductor device generally includes a metal layer disposed on the dielectric layer and having a plurality of metal routings, each of the metal regions disposed over both the first metallization region and the second metallization region, each of the plurality of metal routings have a same width. The semiconductor device generally includes an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the metal routings of the metal layer.