BEOL Upper Metal Line Layout Using Ru and Cu to Cut Resistance
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in reducing interconnect resistance in the back-end-of-line (BEOL) region, particularly due to the increased resistivity of copper (Cu) in narrow metal lines below ten nanometers.
Innovation Solution
The use of both ruthenium (Ru) and copper (Cu) as upper metal lines in the BEOL region, with Ru used in narrow lines and Cu in wider lines, to take advantage of their respective low resistivity properties at different widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metals are used for upper metal lines, then interconnect resistance is reduced, but the fabrication process complexity increases
Solution Approach 1:
The patent segments the upper metal line formation process into distinct regions based on line width. Narrow lines are formed with ruthenium while wider lines are formed with copper, allowing each segment to be optimized independently for its specific electrical performance requirements.
Solution Approach 2:
The patent employs a composite material strategy by integrating two different metals (ruthenium and copper) within the same upper metal line layer. This composite approach allows the interconnect structure to leverage the advantages of each material: ruthenium for narrow lines with low resistivity at small dimensions, and copper for wider lines with inherently low resistivity.
Data Source
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AI summary
Integrated circuit (IC) devices are provided. An IC device includes a back-end-of-line (BEOL) region that includes a first via and a second via on a first lower metal line and a second lower metal line, respectively. The BEOL region includes a first upper metal line coupled to the first lower metal line by the first via, and a second upper metal line coupled to the second lower metal line by the second via. The first upper metal line and the first via each include a first metal. The second upper metal line and the second via each include a second metal that is different from the first metal. Moreover, the second upper metal line is wider than the first upper metal line. Related methods of forming BEOL regions of IC devices are also provided.