BEOL Spacer Interconnect Patterning for Tight-Pitch Self-Aligned Vias
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in patterning extremely small vias with tight pitches and critical dimensions, which exceeds the resolution capabilities of current lithographic technologies, leading to issues with overlay tolerance, line width roughness, and critical dimension uniformity.
Innovation Solution
The proposed solution involves a subtractive plug and tab patterning method using photobuckets for back end of line (BEOL) spacer-based interconnects, which enables self-aligned fabrication of conductive tabs and non-conductive plugs, improving interconnect density and reducing vertical real estate consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern vias, then the manufacturing process is simple and well-established, but the resolution capability is insufficient for extremely small via sizes and tight pitches
Solution Approach 1:
The patent segments the via formation process into multiple discrete steps: forming mandrels at a first pitch, depositing spacers, selectively removing mandrels and spacers, and repeating the process. This segmentation enables achieving sub-lithographic pitch dimensions (e.g., 70-90 nm or less) by dividing the patterning into sequential operations, each operating at relaxed dimensions while collectively producing ultra-fine features.
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels and spacers that define future via locations before actual via etching. The spacer-based self-aligned multiple patterning (SAMP) process pre-establishes the via pitch and position through mandrel and spacer formation, enabling subsequent via holes to be automatically aligned without requiring high-precision overlay during the final via formation step.
2Quantity of substance
If via pitch is reduced to increase density, then interconnect density improves, but overlay tolerance requirements become increasingly stringent
Solution Approach 1:
The patent implements self-alignment mechanisms where spacers automatically define the positions of subsequent features relative to previous features. The spacers are deposited conformally on mandrels and then anisotropically etched to create self-aligned patterns, eliminating the need for external alignment steps. This self-service approach ensures that via holes are automatically positioned with high precision relative to metal lines and other vias, maintaining overlay tolerance even as pitch decreases.
3Quantity of substance
If via critical dimension is reduced to increase density, then interconnect density improves, but line width roughness and critical dimension uniformity deteriorate
Solution Approach 1:
The patent changes the physical and chemical parameters of the photoresist and etching processes to maintain LWR and CDU characteristics. This includes using specialized photoresist formulations, optimizing exposure and development parameters, and adjusting etch chemistry and conditions. These parameter changes enable the formation of ultra-fine via holes with controlled roughness and uniform dimensions, preventing degradation even as critical dimensions scale to 35 nm or less.
Data Source
AI summary
Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.