BEOL Spacer Interconnect Patterning for Fine-Pitch Via Alignment
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Solution Overview
Problem
The scaling of features in integrated circuits poses challenges in overlay control and resolution capabilities for extremely small vias with small pitches, as current lithographic processes struggle to maintain precision and efficiency, especially below 70-90 nanometers, leading to issues with line width roughness and critical dimension uniformity.
Innovation Solution
The implementation of subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects, which uses a textile processing scheme with selective hardmasks and photobucketing to achieve self-aligned conductive tabs and vias, reducing vertical real estate consumption and improving density and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern vias at small pitches (70-90 nm or less), then via pitch and critical dimension scaling is achieved, but overlay control precision deteriorates due to tolerances scaling faster than lithographic equipment capabilities
Solution Approach 1:
The patent applies segmentation by dividing the via patterning process into multiple steps: first forming mandrels at a relaxed pitch, then using spacer-based pitch division to create the final fine-pitch via pattern. This multi-stage approach allows each step to operate at achievable precision levels while achieving the cumulative effect of fine-pitch patterning.
Solution Approach 2:
The patent uses preliminary action by pre-forming mandrels and spacers before the final via etch. The spacers are deposited and patterned in advance to define the exact via locations, ensuring precise overlay control is built into the structure before the critical via formation step occurs.
2Length of moving object
If via critical dimensions are scaled down to maintain density, then via size decreases, but resolution capabilities of lithographic scanners deteriorate as critical dimensions fall below scanner resolution limits
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate between the lithographically-defined mandrels and the final via openings. The spacers act as a self-aligned mask that defines via locations with precision determined by spacer thickness rather than direct lithography, effectively decoupling the via critical dimension from scanner resolution limits.
Solution Approach 2:
The patent replaces direct lithographic definition of via openings with a spacer-based mechanical self-alignment mechanism. Instead of relying on lithographic resolution to directly pattern the via openings, the mechanical deposition and etching of spacers and mandrels defines the final pattern, substituting a mechanical self-aligned process for a lithography-limited process.
3Length of moving object
If multiple lithographic masks are used to achieve extremely small via pitches below scanner resolution, then via pitch scaling is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies universality by using spacers that serve multiple functions: they act as alignment references, as etch masks for via formation, and as definitions for the final via pitch. This multi-functional spacer approach consolidates what would otherwise require multiple separate lithographic masks into a single integrated process flow.
Data Source
AI summary
Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.