BEOL Stacked Analog Components for High-Density RLC Integration
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the difficulty in increasing the density of analog circuitry, such as resistors, capacitors, and inductors, in the Back-End-Of-Line (BEOL) processing due to the limited space and the disparity in density increase compared to digital circuitry as technology nodes scale down.
Innovation Solution
A method involving the formation of conductive members and dielectric layers to create high-density RLC integrated circuits, where conductive vias and filler dielectric materials are used to define resistors and capacitors within the BEOL, allowing for enhanced analog circuit density through multi-level metal component stacks and efficient use of chip surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional BEOL processing is used to form analog components, then the manufacturing process is simple, but the analog circuitry density is insufficient to match the increasing digital circuitry density
Solution Approach 1:
The patent transitions from planar 2D analog component layout to 3D vertical stacking in the BEOL metal layers. Multiple analog components (resistors, capacitors, inductors) are stacked vertically across different metal layers, with conductive vias providing inter-layer connections. This dimensional transition enables significantly higher analog circuitry density without proportionally increasing lithography complexity.
Solution Approach 2:
The patent implements nested stacking where smaller conductive members are positioned within the footprint of larger ones across different metal layers. For example, a second conductive member in a lower metal layer can be nested within the lateral boundaries of a first conductive member in an upper metal layer, creating compact vertical structures that maximize space utilization and component density.
2Area of stationary object
If more analog components are integrated in BEOL to match digital density, then the chip surface area is reduced, but the lithography tool capabilities must be enhanced
Solution Approach 1:
By moving from 2D planar integration to 3D vertical stacking, the patent reduces the lateral footprint required for analog components. The stacking approach utilizes the vertical dimension (multiple metal layers) to accommodate more components, thereby reducing chip surface area without demanding higher lateral lithography precision.
Solution Approach 2:
The patent segments analog components across multiple BEOL metal layers, with each layer containing a subset of the analog circuitry. This segmentation allows standard lithography tools to process each layer independently at relaxed precision requirements, while the cumulative effect across layers achieves high overall component density and reduced surface area.
3Quantity of substance
If conventional analog component formation is used, then the manufacturing cost is lower, but the space utilization for analog components is insufficient
Solution Approach 1:
The patent employs the existing BEOL metal layers and standard fabrication processes (conductive material deposition, patterning, via formation) to create multiple types of analog components (resistors, capacitors, inductors) simultaneously. This multi-functional use of conventional manufacturing steps increases analog component quantity without proportionally increasing manufacturing cost.
Solution Approach 2:
The vertical stacking approach utilizes unused vertical space in the BEOL structure to accommodate additional analog components. By stacking components across multiple metal layers rather than spreading them laterally, the patent increases component quantity while using existing manufacturing processes, thereby maintaining cost-effectiveness.
Data Source
AI summary
A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.